Modeling of Power Supply Noise in Large Chips Using the Circuit-Based Finite-Difference Time-Domain Method (original) (raw)

This paper describes the effect of substrate loss on simultaneous switching noise (SSN) in on-chip power distribution networks (PDN). Conformal mapping and first-order Debye approximation based Finite Difference Time Domain (FDTD) have been used for model extraction and time domain simulation with frequency dependent parameters, respectively. The importance of substrate loss on power supply noise has been quantified in this paper.