Low Power & Area Efficient 16 Bit Carry Select Adder Based On Adiabatic Logic (original) (raw)
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IJERT-Low Power & Area Efficient 16 Bit Carry Select Adder Based On Adiabatic Logic
International Journal of Engineering Research and Technology (IJERT), 2013
https://www.ijert.org/low-power-area-efficient-16-bit-carry-select-adder-based-on-adiabatic-logic https://www.ijert.org/research/low-power-area-efficient-16-bit-carry-select-adder-based-on-adiabatic-logic-IJERTV2IS70772.pdf Adders are of fundamental importance in a wide variety of digital systems. Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. A new CMOS logic family called ADIABATIC LOGIC, based on the adiabatic switching principle is presented. In this paper current parameter of carry select adder will be reduced using adiabatic logic which in turn will reduce heat dissipation of the circuit. Proposed work shows better performance in terms of delay, area & power. Simulation & implementation is based on TannerV13 tool with 0.18µm CMOS process technology.
International Journal of Information Technology and Computer Science, 2013
Addition forms the basic structure for many processing operations like counting, multip licat ion, filtering etc. Adder circuits that add two binary numbers are of great interest for many designers. The simp lest approach to design an adder is to imp lement gates to yield the required logic function. Carry-look ahead adder is a major functional b lock in arith metic logic unit due to its high speed operation. The arithmet ic logic unit has been widely used in microprocessor systems and mostly in processing modules of embedded systems. Therefore, it is of interest to study the functional behavior and power consumption carry-look ahead adder. In this project, the adder is imp lemented using 180 n m CM OS technology on bulk substrate. Two logic families i.e. static CM OS and adiabatic logic have been analyzed and implemented to study the transient characteristics of the adder. Finally the power consumption is estimated and co mpared. Fro m the results it has been found that the static CMOS logic offers low delay whereas the adiabatic logic consumes low power.
Most important design consideration in integrated circuit after power is speed. Adders are one of the basic fundamental components in any digital systems. Due to rapid growth in technology there is need for fast processing. Addition is a basic operation in any digital, analog or control system, fast and accurate operation of digital system depends on the performance of adder. The major problem for binary addition is the propagation delay in the carry chain. As the width of the input operands increases the length of the carry chain will be increased. To reduce the carry propagation problem most of the modern adder architectures are represented as a parallel prefix adder structure. Kogge-Stone adder is one among the parallel prefix adders. This has the regular layout which makes them attractive adder in electronic technologies. This paper proposes the design of Carry Select Adder using Kogge-Stone adder in adiabatic logic. Specifically Positive Feedback Adiabatic Logic (PFAL) is used; this design will have proficiency of energy saving by reusing the energy which helps in reduction of power dissipation. Hence an efficient adder with low power dissipation is designed.
Study of performance of Adiabatic Carry Look Ahead Adder Using Dynamic CMOS Logic
International Journal of Electronics and Electical Engineering, 2012
Performance of adiabatic carry look ahead adder using dynamic CMOS are studied and compared with Adiabatic carry look ahead adder using Pass Transistor. adiabatic carry look ahead adder using pass transistor has higher delay and lower power consumption while adiabatic carry look ahead adder using dynamic cmos logic has lower power dissipation and higher speed. adiabatic carry look ahead adder using dynamic cmos are design using 180 nm cmos technology and compared power dissipation and delay with respect to supply voltage and frequency. simulation result show that power dissipation of carry look ahead adder using dynamic cmos has higher performance comparison adiabatic CLA using pass transistor. simulation result show that adiabatic CLA using dynamic cmos reduce the power consumption 45% and delay reduce to 70% comparison to adiabatic CLA using pass transistor.
Design of energy efficient carry lookahead adder using novel CSIPGL adiabatic logic circuit
Journal of Physics: Conference Series, 2020
This paper presents a novel energy efficient logic called Charge Sharing Improved Pass Gate Adiabatic Logic (CSIPGL) operating using four phase power clock sources. The CSIPGL based circuit is capable of operating through a wider range of frequency from 100MHz to 1GHz. CSIPGL logic has been designed using UMC 90nm technology model files and are simulated using Cadence® Virtuoso EDA tools. Efficiency of CSIPGL circuit is validated by comparing it against CSSAL, SQAL, SyAL, adiabatic logic circuits based on single charge sharing transistor [14] and EE-SPFAL circuit designs. Power consumption of AND/NAND and XOR/XNOR sub modules used in the design of 4-bit Carry Lookahead Adder circuits (CLA) are compared. 4-bit CLA is taken as a benchmark circuit to validate the efficiency of the proposed CSCPAL circuit.
Design and Analysis of Full Adder Using Adiabatic Logic
2016
Power dissipation is an increasing concern in VLSI circuits. New logic circuits have been developed to meet these power requirements. Power dissipation can be minimized by using various adiabatic logic circuits. In this paper an Adder circuit has been proposed based on 2PASCL and ECRL logic and then compared with Positive Feedback Adiabatic Logic(PFAL), Two-Phase Adiabatic Static Clocked Logic(2PASCL) respectively. Comparison shows significant power saving.
Design of Low Power Carry Look-Ahead Adder Using Single Phase Clocked Quasi-Static Adiabatic Logic
IOSR journal of VLSI and Signal Processing, 2014
Efficiency of adiabatic circuits is determined by the adiabatic and non-adiabatic losses incurred by them during the charging and recovery operations. Lesser be the losses more energy efficient would be the circuit. In this paper, a new approach i.e., Complementary Energy Path Adiabatic Logic (CEPAL), is presented to minimize power dissipation in quasi static energy recovery logic (QSERL). It optimizes circuit, by avoiding non-adiabatic losses completely by replacing the diodes with MOSFETs. MOSFET gates are controlled by power clocks and this is implemented in Carry Look-Ahead Adder structure. Firstly, the performance attributes of CEPAL Carry Look-Ahead Adder are compared against the conventional static CMOS logic counterpart to identify its adiabatic power advantage. The analyses are carried out using the industry standard Tanner EDA design environment using 250nm technology libraries. The results prove that CEPAL adiabatic Carry Look-Ahead Adder results in 56.05% of power savings over static CMOS.
Implementation of Low Power and Area-Efficient Carry Select Adder
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32- ,-b square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in 0.18-m CMOS process technology. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.
Low Power and Area-Efficient Carry Select Adder by K.Saranya
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in 0.18-m CMOS process technology. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.
A Novel Approach OF Low Power and Area Efficient Carry Select Adder
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only as light increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in 0.18-m CMOS process technology. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.