A Sizing Methodology for Rise-Time Minimization of Dickson Charge Pumps With Capacitive Loads (original) (raw)

Design Topologies of a CMOS Charge Pump Circuit for Low Power Applications

Electronics

Applications such as non-volatile memories (NVM), radio frequency identification (RFID), high voltage generators, switched capacitor circuits, operational amplifiers, voltage regulators, and DC–DC converters employ charge pump (CP) circuits as they can generate a higher output voltage from the very low supply voltage. Besides, continuous power supply reduction, low implementation cost, and high efficiency can be managed using CP circuits in low-power applications in the complementary metal-oxide-semiconductor (CMOS) process. This study aims to figure out the most widely used CP design topologies for embedded systems on the chip (SoC). Design methods have evolved from diode-connected structures to dynamic clock voltage scaling charge pumps have been discussed in this research. Based on the different architecture, operating principles and optimization techniques with their advantages and disadvantages have compared with the final output. Researchers mainly focused on designing the cha...

On the design of power- and area-efficient Dickson charge pump circuits

Analog Integrated Circuits and Signal Processing, 2014

This paper aims at investigating some methods for designing an area-and power-efficient Dickson charge pump circuit for on-chip high-voltage source generation. A comprehensive study on two conventional methods, with one of them based on optimizing the number of stage for minimum silicon area (minimum area method) and the other for maximum power efficiency (optimal power method), will be presented by considering both top-and bottom-plate parasitic capacitances. It was found that when the parasitic factors are as large as 0.1, the area and power efficiencies of the charge pumps designed with either the optimal power or minimum area method do not have much degradation. However, when the parasitic factors are small, charge pumps designed with the optimal power and minimum area methods can, respectively, result in a large area and poor power efficiency. The power efficiency of the charge pump designed with the minimum area method may be reduced by 50 %, while the area of the charge pump designed with the optimal power method can be 1-2 times larger, when the parasitic factors are 0.01. Hence, neither the optimal power nor minimum area methods should be used when the parasitic factors are small, unless the power or area is the only concern in the design. With this con-nection, the number of stage which leads to an area and power-efficient charge pump is suggested. Validity was proved by the good agreement between the simulated and the expected results for some designed charge pump circuits of the proposed design strategy.

A 5 V to 180 V Charge Pump for Capacitive Loads in a 180 nm SOI Process

Elektronika ir Elektrotechnika, 2021

This paper presents two variants of a high step-up ratio charge pump for high voltage micro electro-mechanical system and condenser microphones. The implementations are based on an additive charge pump topology where respectively 46 and 57 cascaded stages are used to generate an output voltage of 182 V from a supply voltage of 5 V. The two charge pumps have been fabricated in a 180 nm SOI process with a breakdown voltage of more than 200 V and respectively occupy an area of 0.52 mm2 and 0.39 mm2. The charge pumps can output up to 182.5 V and 181.7 V and are designed to drive a capacitive load with a leakage of 2 nA. When driven with a 100 kHz clock, their power consumption is respectively 40 µW and 20 µW. The rise time of the charge pumps output from 0 V to 182 V is less than 5 ms. The implemented charge pumps exhibit state-of-the-art performance for very high voltage dc-dc capacitive drive applications.

DESIGN, IMPLEMENTATION AND COMPARISON OF VARIOUS CMOS CHARGE PUMPS

A charge pump is a kind of DC to DC converter that uses capacitors as energy storage elements to create a higher or lower voltage power source. Charge pumps make use of switching devices for controlling the connection of voltage to the capacitor. The use of charge transfer switches (CTSs) can improve the voltage pumping gain. Applying dynamic control to the CTSs can reduce reverse currents. This paper includes voltage and power analysis of various charge pump circuits. And a comparison is drawn between the three charge pumps analyzed.

Charge Pump Circuits for Low-voltage Applications

VLSI Design, 2002

In this paper, a low-voltage, high performance charge pump circuit, suitable for implementation in standard CMOS technologies is proposed. Its pumping operation is based on cascading several crossconnected NMOS voltage doubler stages. For very low-voltage applications (1.2 V, 0.9 V), where the performance of the NMOS transistors is limited due to body effect, two improved versions of the charge pump with cascaded voltage doublers (charge pump with CVD) are also proposed. The first utilises PMOS transistors (charge pump with CVD-PMOS) in parallel to the cross-connected NMOS transistors, while the second improves the pumping gain by boosting the clock amplitude (charge pump with CVD-BCLK). Simulations at 50 MHz have shown that a five-stages charge pump with CVD can achieve a 1.5-8.4 V voltage conversion. For the same stage number and frequency, an output voltage of 4 and 7.3 V can be generated from 0.9 V, by using the charge pump with CVD-PMOS and the charge pump with CVD-BCLK, respectively.

A CMOS charge pump for low voltage operation

2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353), 2000

This paper proposes a low-voltage, high performance charge pump circuit suitable for implementation in standard CMOS technologies. The proposed charge pump utilises the cross-connected NMOS, voltage doubler, as a pumping stage. For low-voltage operation, where the performance of the NMOS is limited due to body effect, PMOS are used to increase the pumping gain. Simulations at 50 MHz have shown that for power supply voltages of 2V, 1.5V, 1.2V and 0.9V an output voltage of I1.5V, 8.4V, 6.5V and 4V can be generated respectively, using five pumping stages.

A CMOS high-voltage DC-DC up converter dedicated for ultrasonic applications

4th IEEE International Workshop on System-on-Chip for Real-Time Applications

This paper concerns the design and implementation of a fully integrated High Voltage CMOS DC-DC Up Converter (VHVUC) dedicated to ultrasonic transmitters. This VHVUC new topology, followed by a drive amplifier, is based on a multiplestage charge pump circuit and a level-up Shifter is used in each stage as a clock generator in order to increase exponentially the DC voltage. A drive amplifier, based on a level-up stage and a class D switching output stage. It is used to excite the ultrasonic transducer, resonate at 3.5 MHz. Simulation results of the proposed converter, using a 0.8µm CMOS/DMOS High-Voltage process technology, show output voltage of 200 V with 83% gain voltage factor and a 95 mV output ripples for 2 MHz frequency. Also, the drive amplifier for single shock excitation show a 140 V spike at the transducer element with a pulse repetition time of 260µs and a rise and fall times of 220 ns and 713 ns respectively with a peak current through the transducer element of 25 mA. These results show the feasibility of applying HV process technology to replace conventional electronic transmitter technology.

Power efficient charge pump in deep submicron standard cmos technology

IEEE Journal of Solid-State Circuits, 2003

A power efficient charge pump is proposed. The use of low voltage transistors and of a simple 2-phase clocking scheme allows the use of higher frequencies compared to conventional solutions, thus obtaining high current, high efficiency and small area. Measurements show good results for frequencies around 100MHz.

Analysis of Charge Pump Topologies for High Voltage Mobile Microphone Applications

Elektronika Ir Elektrotechnika, 2021

This paper presents a novel analysis of charge pump topologies for very high voltage capacitive drive micro electro-mechanical system microphones. For the application, the size and power consumption are sought to be minimized, and a voltage gain of 36 is achieved from a 5 V supply. The analysis compares known charge pump topologies, taking into consideration on resistance of transistors and parasitic capacitances of transistors and capacitors in a 180 nm siliconon-insulator process. The analysis finds that the Pelliconi charge pump topology is optimal for generating very high bias voltages for micro electro-mechanical system microphones from a low supply voltage when the power consumption and area are limited by the application.

Novel CMOS Bulk-driven Charge Pump for Ultra Low Input Voltage

Radioengineering, 2016

In this paper, a novel bulk-driven cross-coupled charge pump designed in standard 90 nm CMOS technology is presented. The proposed charge pump is based on a dynamic threshold voltage inverter and is suitable for integrated ultra-low voltage converters. Due to a latchup risk, bulkdriven charge pumps can safely be used only in low-voltage applications. For the input voltage below 200 mV and output current of 1 µA, the proposed bulk-driven topology can achieve about 10 % higher efficiency than the conventional gate-driven cross-coupled charge pump. Therefore, it can be effectively used in DC-DC converters, which are the basic building blocks of on-chip energy harvesting systems with ultra-low supply voltage.