Harnessing VLSI System Design with EDA Tools (original) (raw)

Intelligent design automation of VLSI interconnects

Eleventh Annual International Phoenix Conference on Computers and Communication [1992 Conference Proceedings], 1992

Interconnection and packaging are among the dominant factors that limit the performance of future integrated circuits containing millions of transistors. As chips become more complex, so does the packaging. Design automation is thus without doubt necessary. In this paper, a window based simulation environment called PDSE (Packaging Design Support Environment) which integrates several tools for VLSI interconnection modeling and simulations is presented. We will describe the concept of the automated packaging design cycle, the structure and the components of the simulation environment, and the implementation of an interconnect layout geometry data extractor. Finally a case study will be given to illustrate the entire design process.

The Design of VLSI Design Methods

The Mead-Conway VLSI design and implementation methodologies were deliberately generated to be simple and accessible, and yet have wide coverage and efficiency in application. An overview is given of the methods used to "design the design methodology." We sketch the results and the status of these methods, and of the associated infrastructure of university courses, computer network communities, silicon implementation systems, and silicon foundries in the United States.

Comparative Analysis of Open-Source EDA Tool for VLSI Physical Design

Open-source EDA tools are becoming very popular nowadays and they are also becoming more efficient. Academic researchers can use these open-source EDA tools which are free of cost and still give the idea about the whole chip design flow. These open-source EDA tools can also be used for real chip tap out so we can also manufacture a chip with the layout made with such tools. Commercial tools require very high license costs and are used in industries for high efficiency. The arithmetic and Logic Unit is the fundamental building block in any processor which performs arithmetic and logical operations. ALU is widely used for signal processing tasks where lots of additions and multiplications need to be performed at very high speed and also in communication-related applications. In this paper, the whole flow of chip design is performed on 8-bit ALU with both open-source tools that are Qflow and commercial tool that is Cadence Encounter. The RTL design is first written in Verilog and also functionally verified. Then Synthesis is done which converts RTL code into a gate-level netlist. Then different physical design steps like partitioning, floorplanning, power planning, placement, CTS, routing, timing closure are performed. After STA, LVS, DRC, the final layout is generated that is GDS-II file which can be given for tape out. The 180nm technology node is used in the physical design. With so many advantages of open-source tools, to know how efficient they are, design is done in Qflow and Cadence Encounter. Results are compared based on area, speed, and power which are the most important parameters in VLSI design. From the result, it can be seen that the area requires in design made with Qflow is almost 4 times larger than the design made with Cadence Encounter. Power required for design with Qflow is 25 times higher than design with Cadence Encounter.

A methodology and design tools to support system-level VLSI design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1995

System-level design involves making major design decisions without having accurate information on the eventual system characteristics. This paper presents a novel constraintdriven methodology to support system-level design. The software assists a designer or a tool in partitioning behavioral specifications onto multiple VLSI chips and in system design while satisfying hard constraints such as individual chip areas, chip pin counts, system throughput (inverse of system initiation interval) and system latency (delay). The software uses search and estimation techniques to perform comprehensive design-space exploration and evaluates partitions supplied by the user or by other synthesis software. The technique determines what design characteristics each partition must possess in order to satisfy area, pin, throughput and latency constraints. The paper also includes results of extensive experiments with the methodology.

Physical Design Automation of Complex ASICs

Physical Designs of Application Specific Integrated Circuits (ASICs) is a challenging and paradigmatic process as the resources are limited or difficult to find. This paper shows the fundamental steps of Physical Design with the use of Electronic Design Automation (EDA) tools like Nitro-SoC and Olympus- SoC of Mentor Graphics. In order to illustrate the Place and Route flow, experiments were carried out using a test circuit and the results of each flow step performed were displayed with snapshots. Although the intent of this paper is to put forward a technical approach for mastering ASICs' back-end design in more details and engage engineers in practices, designers in the progression of the Physical Design of a complex chip may also get benefits from it, since it answers the central questions faced at the advanced nodes SoCs. This hands-on flow steps will be an added advantage, besides the traditional Place and Route (PnR) flow. It will also help professional scientist and engineers to enhance their skills and expertise in the back-end design, and to analyze and fix ASIC circuits.

Chapter 38 , Design Automation for Microelectronics , Springer Handbook of Automation

2009

Design automation or computer-aided design (CAD) for microelectronic circuits has emerged since the creation of the integrated circuits (IC). It has played a crucial role to enable the rapid development of hardware and software systems in the past several decades. CAD techniques are the key driving forces behind the reduction of circuit design time and the optimization of the circuit quality. Meanwhile, the exponential growth of circuit capacity driven by the Moore’s law prompts new and critical challenges for CAD techniques. In this chapter we will introduce the fundamentals of design automation as an engineering field. We begin with several important processor technologies and several existing IC technologies. We then present a typical CAD flow covering all the major steps in the design cycle. We also cover some important topics such as verification and TCAD. Finally, we introduce some new trends in the design automation field.

Survey on Design Automation and Verification for VLSI Circuits

International Journal of Research and Analytical Reviews (IJRAR), 2023

The field of Very Large-Scale Integration (VLSI) has developed throughout the course of recent many years and has turned into a critical empowering innovation for an extensive variety of current gadgets. The integration of millions of transistors onto a single chip in VLSI design poses a significant challenge in terms of verification complexity. Design automation and verification has emerged as a significant area of research and development An overview of design automation and verification for VLSI circuit design is the goal of this paper. We'll talk about the difficulties encountered during the design process and how design automation and verification methods can be used to overcome them. also look at the many tools, methods, and processes utilized in VLSI circuit design for design automation and verification. Finally, we will look at recent advancements in this area and the forecast for design automation and circuit verification for VLSI devices in the future

An integrated system for design automation of VLSI interconnects and packaging

The packaging design support environment (PDSE) is a software system being developed at the University of Arizona to facilitate the analysis and design of packaging structures for microelectronic integrated circuits, a subject which is becoming one of increasing iruportance with higher circuit integration and system perfor1nanc.e. PDSE provides a platform for work in several active research areas including interconnect and packaging modeling and simulation in electrical, thermal, and thermal-mechanical aspects, ('AD framework development and evaluations for performance, riianufacturability, and reliability, etc. This paper describes the overall architecture and characteristics of the PDSE system in development, its implementation and applications.

Technology transfer between VLSI design and software engineering: CAD tools and design methodologies

Proceedings of the IEEE, 1986

Recent research on the explicit transfer of technology used in computer-aided design (CAD) tools and design methodologies is reported. First, several examples are given of applications of these technologies to software engineering. Then, three research projects are described which focused on applying software engineering principles to the VLSl design process. They are: a methodology, language, and assessment tool for multilevel mixed-mode VLSl designs; a research project that explored the potential for transfer of software design methodologies for managing VLSI design complexity; and a specification technique for "modules" in a VLSl design that localizes the impact of changes to the design. Next, a CAD tool and design methodology are described which consider the design of software and hardware together, and apply common techniques to both. Finally, some observations are made on the appropriateness of technology transfer between VLSI design and software engineering.