A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR) (original) (raw)

Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

Journal of Computers, 2009

The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range. Such inversely proportional decline in size and boost in performance consequently demands shrinking of supply voltage and effective power dissipation in chips with millions of transistors. This has triggered substantial amount of research in power reduction techniques into almost every aspect of the chip and particularly the processor cores contained in the chip. This paper presents an overview of techniques for achieving the power efficiency mainly at the processor core level but also visits related domains such as buses and memories. There are various processor parameters and features such as supply voltage, clock frequency, cache and pipelining which can be optimized to reduce the power consumption of the processor. This paper discusses various ways in which these parameters can be optimized. Also, emerging power efficient processor architectures are overviewed and research activities are discussed which should help reader identify how these factors in a processor contribute to power consumption. Some of these concepts have been already established whereas others are still active research areas.

Enhancing sensitivity-based power reduction for an industry IC design context

Integration, 2019

For many years, discrete gate sizing has been widely used for timing and power optimization in VLSI designs. The importance of gate sizing optimization has been emphasized by academia for many years, especially since the 2012/2013 ISPD gate sizing contests [1, 2]. These contests have provided practical impetus to academic sizers through the use of realistic constraints and benchmark formats. At the same time, due to simplified delay/power Liberty models and timing constraints, the contests fail to address real-world criteria for gate sizing that are highly challenging in practice. We observe that lack of consideration of practical issues such as electrical and multi-corner constraints-along with limited sets of benchmarks-can misguide the development of contestfocused academic sizers. Thus, we study implications of the "gap" between academic sizers and product design use cases. In this paper, we note important constraints of modern industrial designs that are generally not comprehended by academic sizers. We also point out that various optimization techniques used in academic sizers can fail to offer benefits in product design contexts due to differences in the underlying optimization formulation and constraints. To address this gap, we develop a new robust academic sizer, Sizer, from a fresh implementation of Trident [3]. Experimental results show that Sizer is able to achieve up to 10% leakage power and 4% total power reductions compared to leading commercial tools on designs implemented with foundry technologies, and 7% leakage power reduction on a modern industrial design in the multi-corner multi-mode (MCMM) context.

Power Optimization Techniques Adopted at various Abstraction Levels in System on Chip Design -A Survey

International Journal For Research In Applied Science & Engineering Technology, 2020

To meet the requirements of consumers the portable electronic devices are embedded with advanced integrated System on Chip (SoC) Circuits. The complex SoC's are power hungry and needs power optimization at various levels of the chip design. Based on the observation of the power consumption, the optimization has become a real issue, and may also be the limiting factor of future growth. This paper provides the details of different types of power dissipation and their major causes. Further, the paper focus on the different aspects in which power can be optimized. The beginner gets an idea during the design flow what are the causes of power consumption and at which level of abstraction need to be concentrated to reduce power. It also provides advantage and disadvantages associated with power optimization. And summary describes which abstraction levels results in how much power savings and error percentage.

Survey on Power Optimization Techniques for Low Power VLSI Circuit in Active & Standby Mode of Operation

CMOS technology is the key element in the development of VLSI systems since it consumes less power. Power optimization has become an overridden concern in deep submicron CMOS technologies. Due to shrink in the size of device, reduction in power consumption and over all power management on the chip are the key challenges. For many designs power optimization is important in order to reduce package cost and to extend battery life. In power optimization leakage also plays a very important role because it has significant fraction in the total power dissipation of VLSI circuits. This paper aims to elaborate the developments and advancements in the area of power optimization of CMOS circuits in deep submicron region. This survey will be useful for the designer for selecting a suitable technique depending upon the requirement.

Analysis of Power Dissipation & Low Power VLSI Chip Design

Low power requirement has become a principal motto in today’s world of electronics industries. Power dissipation has becoming an important consideration as performance and area for VLSI Chip design. With reducing the chip size, reduced power consumption and power management on chip are the key challenges due to increased complexity. Low power chip requirement in the VLSI industry is main considerable field due to the reduction of chip dimension day by day and environmental factors. For many designs, optimization of power is important as timing due to the need to reduce package cost and extended battery life. This paper present various techniques to reduce the power requirement in various stages of CMOS designing i.e. Dynamic Power Suppression, Adiabatic Circuits, Logic Design for Low Power, Reducing Glitches, Logic Level Power Optimization, Standby Mode Leakage Suppression, Variable Body Biasing, Sleep Transistors, Dynamic Threshold MOS, Short Circuit Power Suppression.

Survey on Power Optimization Techniques for Low PowerVLSI Circuitsin Deep Submicron Technology

International Journal of VLSI Design & Communication Systems, 2018

CMOS technology is the key element in the development of VLSI systems since it consumes less power. Power optimization has become an overridden concern in deep submicron CMOS technologies. Due to shrink in the size of device, reduction in power consumption and over all power management on the chip are the key challenges. For many designs power optimization is important in order to reduce package cost and to extend battery life. In power optimization leakage also plays a very important role because it has significant fraction in the total power dissipation of VLSI circuits. This paper aims to elaborate the developments and advancements in the area of power optimization of CMOS circuits in deep submicron region. This survey will be useful for the designer for selecting a suitable technique depending upon the requirement.

Strategies & Methodologies for Low Power Vlsi Designs: A Review

1963

Low power has emerged as a principal theme in today's world of electronics industries. Power dissipation has become an important consideration as performance and area for VLSI Chip design. With shrinking technology reducing power consumption and over all power management on chip are the key challenges below 100nm due to increased complexity. For many designs, optimization of power is important as timing due to the need to reduce package cost and extended battery life. For power management leakage current also plays an important role in low power VLSI designs. Leakage current is becoming an increasingly important fraction of the total power dissipation of integrated circuits. This paper describes about the various strategies, methodologies and power management techniques for low power circuits and systems. Future challenges that must be met to designs low power high performance circuits are also discussed.

ASAP: a transistor sizing tool for speed, area, and power optimization of static CMOS circuits

Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94

This paper introduces an automated transistor sizing tool (ASAP) that incorporates accurate gatelevel functio~nal models and can be used for delay, area, and power optimization of CMOS combinational logic circuits in a VLSI design environment. ASAP considers the performailce improvement of VLSI CMOS circuits by optimally sizing the transistors on the first N critical paths. The global picture of the circuit is considered by taking into account the effects that the transi.stor size changes of one path have on the others. The optimization technique in our sizing tool is based on simulated annealing and couples accurate delay modeling with power and area optimization. The combinatorial minimization of the objective function relies on analytical models that can accurately evaluate the delay, the power and the area of a gate. ASAP has been implemented in C on an Apollo 400 workstation with encouraging results.

Analysis of Optimization Techniques for Low Power VLSI Design

With shrinking technology, as power density (measured in watts per square millimetre) is raising at an alarming rate, power management is becoming an important aspect for almost every category of design and application. Reducing power consumption and over all on chip power management are the key challenges in deep sub micro meter nodes due to increased complexity. Power management needs to be considered at very early design stages. Also low-power techniques should to be employed at every design stage, from RTL (Register Transfer Level) to GDSII. This survey paper describes the various strategies, methodologies and power management techniques for low power VLSI circuits. Future challenges that must be met by designers to designs low power high performance circuits are also discussed. State-of-the-art optimization methods at different abstraction levels that target design of low power digital VLSI circuits are surveyed.