Investigation of sub-10nm cylindrical surrounding gate germanium nanowire field effect transistor with different cross-section areas (original) (raw)
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Pefformance and Electrical Charactrization of of Ge-Nanowire Field Effect Transistor
Journal of emerging technologies and innovative research, 2018
In Nanoscale regime some disadvantages are associated with the existing MOSFETs, nanowire FET devices are one of the alternative semiconductor devices which have potential to replace the existing MOSFET technology in future. In this paper a simulation study is reported that how Ge nanowire FET devices can replace the MOSFETs. In devices metallic contacts are considered as source and drain as well as Ge nanowire is considered as a channel between source and drain. Different simulations are performed in nanoHUB with different channel length to analyze the impact of different factors on electronic transport inside the nanowire FETs. Analysis are observed with the scaling the channel length of the nanowire FETs. It is observed through simulation results that at low gate voltage, drain current and the sub-threshold swing increases.
Performance analysis of a Ge/Si core/shell nanowire field-effect transistor
Nano letters, 2007
We analyze the performance of a recently reported Ge/Si core/shell nanowire transistor using a semiclassical, ballistic transport model and an sp 3 s*d 5 tight-binding treatment of the electronic structure. Comparison of the measured performance of the device with the effects of series resistance removed to the simulated result assuming ballistic transport shows that the experimental device operates between 60 to 85% of the ballistic limit. For this ~15 nm diameter Ge nanowire, we also find that 14-18 modes are occupied at room temperature under ON-current conditions with I ON /I OFF =100. To observe true one * Corresponding author Email: liangg@purdue.edu 2 dimensional transport in a <110> Ge nanowire transistor, the nanowire diameter would have to be much less than about 5 nm. The methodology described here should prove useful for analyzing and comparing on common basis nanowire transistors of various materials and structures.
Germanium nanowire field-effect transistors with SiO2 and high-kappa HfO2 gate dielectrics
Applied Physics Letters, 2003
Single-crystal Ge nanowires are synthesized by a low-temperature (275 °C) chemical vapor deposition (CVD) method. Boron doped p-type GeNW field-effect transistors (FETs) with back-gates and thin SiO2 (10 nm) gate insulators are constructed. Hole mobility higher than 600 cm2/V s is observed in these devices, suggesting high quality and excellent electrical properties of as-grown Ge wires. In addition, integration of
Germanium nanowire field-effect transistors with SiO 2 and high-κ HfO 2 gate dielectrics
Single-crystal Ge nanowires are synthesized by a low-temperature ͑275°C͒ chemical vapor deposition ͑CVD͒ method. Boron doped p-type GeNW field-effect transistors ͑FETs͒ with back-gates and thin SiO 2 ͑10 nm͒ gate insulators are constructed. Hole mobility higher than 600 cm 2 /V s is observed in these devices, suggesting high quality and excellent electrical properties of as-grown Ge wires. In addition, integration of high-HfO 2 ͑12 nm͒ gate dielectric into nanowire FETs with top-gates is accomplished with promising device characteristics obtained. The nanowire synthesis and device fabrication steps are all performed below 400°C, opening a possibility of building three-dimensional electronics with CVD-derived Ge nanowires.
In this work we have investigated the impact of quantum mechanical effects on the device performance of n-type in ultra-scaled SixGe1-x nanowire transistors (NWT) for possible future applications. For the purpose of this paper SixGe1-x NWTs with different SixGe1-x molar fraction has been simulated. However, in all devices the cross-sectional area, dimensions and doping profiles are kept constant in order to provide fair comparison. The design of computational experiment in this work includes nanowire transistors with different gate length of 6nm, 8nm, 10nm, 12nm and 14nm. All wires are simulated with various SixGe1-x ratio. As a result we have established a correlation between the mobile charge distribution in the channel and gate capacitance, drain induced barrier lowering (DIBL) and the sub-threshold slope (SS). The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs, is also have been investigated. More importantly all calculations are based on quantum mechanical description of the mobile charge distribution in the channel. This description is based on Schrödinger equation, which is indeed preferred approach for nanowires with such ultra-scale dimensions.
ACS nano, 2017
Germanium is a promising material for future very large scale integration transistors, due to its superior hole mobility. However, germanium-based devices typically suffer from high reverse junction leakage due to the low band-gap energy of 0.66 eV and therefore are characterized by high static power dissipation. In this paper, we experimentally demonstrate a solution to suppress the off-state leakage in germanium nanowire Schottky barrier transistors. Thereto, a device layout with two independent gates is used to induce an additional energy barrier to the channel that blocks the undesired carrier type. In addition, the polarity of the same doping-free device can be dynamically switched between p- and n-type. The shown germanium nanowire approach is able to outperform previous polarity-controllable device concepts on other material systems in terms of threshold voltages and normalized on-currents. The dielectric and Schottky barrier interface properties of the device are analyzed in...
IEEE Transactions on Electron Devices, 2018
The electron mobility in junctionless (JL) and inversion-mode (IM) Ge nanowire nFETs with [110] channel direction is studied by theoretical calculations. Channels with different widths and cross-sectional shapes are compared. The mobility calculation is based on the Kubo-Greenwood formulation for 1-D systems. Phonon scattering, Coulomb scattering (CS), and surface roughness scattering (SRS) are considered. With the equivalent oxide thickness of 1 nm, diamond and square channels have the higher mobility than circular channels at low channel carrier density, but the lower mobility at high channel carrier density for both JL and IM channels. This mobility trend is explained by the SRS on the sharp corners in diamond and square channels. The JL channels have the lower mobility than IM channels at low channel carrier density due to additional CS. At high channel carrier density, SRS dominates, and the JL channel has the slightly higher mobility than the IM channel due to its weaker SRS. The mobility difference between JL and IM is negligible for 5-nm narrow wires. Index Terms-Electron mobility, gate-all-around, germanium, inversion mode (IM), junctionless (JL), nanowire (NW). I. INTRODUCTION T HE advent of FinFET transistors has significantly enhanced the performance and reduced the power consumption of scaled transistors, thanks to the superior electrostatic gate control [1]. The nanowire (NW) MOSFET further improves the gate control by surrounding the channel with the gate stacks [2]. NW devices with various channel crosssectional shapes, such as circle, rectangle, and diamond, have been demonstrated on Si MOSFETs [3], [4].
Ge/Si nanowire heterostructures as high-performance field-effect transistors
Nature, 2006
| Ge/Si core/shell NWFET. a, Schematic of a Ge/Si core/shell nanowire. b, Cross-sectional diagram showing the formation of hole-gas in the Ge quantum well confined by the epitaxial Si shell, where CB is the conduction band and VB is the valence band. The dashed line indicates the Fermi level, E F . The valence band offset of ,500 meV between Ge and Si serves as a confinement potential to the hole-gas as discussed previously 7 . c, Schematic of the NWFET device with high-k dielectric layer and Au top gate. d, Top-view SEM image of a typical device. The Au top gate overlaps with the Ni source/drain electrodes to ensure full coverage of the channel. Scale bar, 500 nm. e, Cross-sectional TEM image of a device prepared using 7 nm ZrO 2 dielectric. Dotted lines are guides to the eye showing boundaries between different materials denoted in the image. The nanowire is tilted off the imaging axis. Scale bar, 10 nm.
Performance Analysis of 20 nm Pentagonal and Trapezoidal NanoWire Transistor with Si and Ge Channel
2016
In this paper, we have analyzed the variability in the performance of Gate All Around Nanowire Field Effect Transistor (GAA NWFET) due to their cross sectional shapes, channel diameter, channel height and channel material with the aid of 3D Technology Computer Aided Design (TCAD) simulations. Pentagonal and trapezoidal Cross sectional shapes have been designed for Si and Ge based channel with different values of diameter and heights. The performance is evaluated in terms of Ion current, switching speed, leakage current, transfer and output characteristics, Subthreshold Swing (SS), Drain Induced Barrier Lowering (DIBL), threshold voltage (Vti) and compared with triangular NWT. After comparison, it shows that Si Pentagonal NWT structure is showing better performance i.e. high on-current, low DIBL and low SS. Ge NWT offers better leakage current. Key-Words: GAA FET; TCAD; NWT; DIBL; SS; Threshold Voltage.