Switching Techniques: Concepts for Low Loss Switching (original) (raw)
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International Journal of Computer Applications, 2011
The most research on the power consumption of circuits has been concentrated on the switching power and the power dissipated by the leakage current has been relatively minor area. In today"s IC design, one of the key challenges is the increase in power dissipation of the circuit which in turn shortens the service time of battery-powered electronics, reduces the longterm reliability of circuits due to temperature-induced accelerated device and interconnects aging processes, and increases the cooling and packaging costs of these circuits. In this paper the main aim is to reduce power dissipation. A new design method for various logical circuits design, which is low power, compared to general Static CMOS logic. In this technique both NMOS transistor and PMOS transistors in various logic circuits is split into two transistors. Leakage current flowing through the NMOS transistor stack reduces due to the increase in the source to substrate voltage in the top NMOS transistor and also due to an increase in the drain to source voltage in the bottom NMOS transistor Leakage current flowing through the PMOS transistor stack reduces due to the increase in the source to substrate voltage in the top PMOS transistor and also due to an increase in the drain to source voltage in the bottom NMOS transistor. The tool used is TANNER EDA for schematic simulation. The simulation technology used is MOSIS 180nm.
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Domino CMOS logic finds a wide variety of applications due to their high speed and low device count. In conventional CMOS domino logic, either the dynamic-node capacitor, CL is precharged to VDD during the precharge phase or predischarged to 0 V. The first precharging scheme is more suitable when logic "0" occurrence is more probable at the output due to the large saving in power consumption. On the other hand, the second predischarging scheme is more suitable when logic "1" is more probable at the output. In this paper, we will propose a novel technique to speed up the operation and minimize power consumption when there is an equal probability of occurrence of logic "0" and logic "1". This technique depends on precharging the dynamic node to VDD/2 instead of VDD during the precharge phase. Then, during the evaluation phase, the dynamic-node voltage will be either increased to VDD or decreased to 0 V depending on the state of the inputs. This, of course, saves much of the time and power consumption because discharging the dynamic node from VDD/2 to 0 V is much faster and consumes less power consumption than discharging it from VDD to 0 V. Also, the discharging process and noise margin will be enhanced by virtue of the fact that the time interval during which the keeper combats the discharging process is relatively very small. The proposed technique will be simulated for the 0.13 mum technology with VDD=1.2 V. Simulation results show that about 75% was shaved from the cycle time for the case of "0" and "1" outputs at the expense of an additional silicon area.
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With the rapidly evolving silicon technology, the power density becomes increasingly high. Quadratically related to power, the voltage scaling offers a means of minimizing energy. However, power supply scaling demands less threshold voltage, which rises leakage current. Several low power techniques have been devised. This chapter deals with the non-conventional low power design solutions, based on adiabatic switching theory. In such circuits, the energy rather than getting dissipated during every cycle, is transferred back and forth between the logic and power-clock sources. A brief discussion on the reversible logic circuits will be presented followed by the fully adiabatic and quasi-adiabatic circuits. The use of power-clock sources for operating the adiabatic circuits will also be introduced. The generalized energetics of an adiabatic circuit followed by the typical loss models of the adiabatic families are presented. Some of the adiabatic circuits employing CMOS transistors are introduced in the chapter. A short comparison for the adiabatic circuit leakage models follows.
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Ibm Journal of Research and Development, 2006
This paper describes a new circuit family—limited switch dynamic logic (LSDL). LSDL is a hybrid between a dynamic circuit and a static latch that combines the desirable properties of both circuit families. The paper also describes many enhancements and extensions to LSDL that increase its logical capability. Finally, it presents the results of two multiplier designs, one fabricated in 130-nm technology and one in 90-nm technology. The 130- and 90-nm designs respectively reach speeds up to 2.2 GHz and 8 GHz.
REDUCING POWER CONSUMPTION OF IC USING LOW POWER BUS ARCHITECTURE
The Low power bus architecture [9, 12, 13] consists of Driver, Receiver and Interconnects in between them inside the Chip. The Low power bus architecture [1] models are classified in to Symmetric and Asymmetric [7, 11, 14, 15] based on low voltage scaling technique and very simple design principles were utilized to construct driver, receiver and interconnects. The low power bus driver has the ability to switch from a low swing to high swing mode. The receiver can be a simple inverter. The bus architecture consists of a driver which has an input the nominal voltage value level and decreases the voltage swing on the bus line (or the output load); and a receiver which regenerates the proper voltage levels in order to ensure the compatibility with the attached circuits. These bus architectures are designed in conventional CMOS technology and Pseudo NMOS technology. These bus architectures were implemented on 2.0V 0.25μm CMOS technology using T-Spice, for signal transmission along a wirelength of 3mm, 6mm, and 10mm and the extra fan-out load of 0.12 pF (on the wire). The performance of each of the presented circuits is thoroughly examined using simulation on a test benchmark interconnect circuit (i) RC─π (N) type (where N = 1, 2, 3), (ii) RC−L type. Comparisons of the proposed architecture with conventional CMOS architecture are presented as well, indicating a significant saving in power due to low voltage scaling. The advantages of the proposed architectures are that they require only one power supply and threshold voltage as well as less area, hence significantly reducing the design complexity. Index Terms-Pseudo NMOS Logic design, Previous and Present Digital CMOS design, 0.25μm technology, Bus architecture, and Interconnect Length, Low Power and Performance tradeoffs.
A Low-Power Circuit Technique for Dynamic CMOS Logic
2011
Dynamic logic style is used in high performance circuit designs because of its faster speed and lesser transistor requirement as compared to static CMOS logic style. Dynamic logic has inherent disadvantages like less noise immunity and high power consumption. In this paper we have proposed a novel circuit technique for implementing dynamic gate. The proposed circuit has very less power dissipation with almost same noise immunity compared to the recently proposed circuit techniques for dynamic logic styles to improve noise immunity. The concept is validated through extensive simulation. Keywords-Domino logic, dynamic logic, power consumption, leakage tolerance, robustness.
24th national convention of Electronics & Communication Engineers & National seminar on Recent Advances in Wireless & Mobile telecommunications -2008 (RAWMTEL-08), 2008
The conventional static CMOS digital circuits consume energy from V dd while making 0→1 transition and stores this energy in C L which is parasitic capacitance composed of diffusion capacitance of driving gate, wire capacitance of the interconnect and the gate capacitance of the fan out gate. This stored energy is dissipated in the pull-down network while the circuit makes a 1→0 transition. Adiabatic switching is a different approach, where the signal energies stored on circuit parasitic capacitances may be recycled instead of being allowed to dissipate as heat. We carry out the study on adiabatic amplifier circuit and analyze its performance. The dissipation of the adiabatic amplifier is compared to that of conventional switching circuits, both for the case of a fixed voltage swing and the case when the voltage swing can be scaled to reduce power dissipation. We carry out the simulations using various load capacitances and propose a developed adiabatic amplifier. All the simulations have been performed in 0.6µm CMOS technology using Cadence Design Systems.