BEOL parametric variation control with FDC data (original) (raw)
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Journal of Dynamic Systems, Measurement, and Control, 2004
Dimensional variation reduction is critical to assure high product quality in discrete-part manufacturing. Recent innovations in sensor technology enable in-process implementation of laser-optical coordinate sensors and continuous monitoring of product dimensional quality. The abundance of measurement data provides an opportunity to develop next generation process control technologies that not only detect process change, but also provide guidelines respective of root cause identification. Given continuous product dimensional measurements, a critical step leading to root cause identification is the variance estimation of process variation sources. A few on-line variance estimators are available. The focus of this paper is to study the interrelationships and properties of the available variance estimators and compare their performance. An operating characteristics curve is developed as a convenient tool to guide the appropriate use of on-line variance estimators under specific circums...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022
There is a consistent dependence between integrated circuits performance parameters and manufacturing process variations and capturing it at an early development phase represents a major ongoing topic in the semiconductor industry. Typically, this is addressed by the means of Monte Carlo simulations, where the device model parameters are randomly instantiated according to the technology variations based on a predefined nominal process. Thus, the resulted simulation data can only capture the effect of these variations. This offers little or no insight on the performance's sensitivities to specific process variations or on the effect of altered statistical technology properties, as it may be the case of process drift or fab-to-fab migration. This paper proposes a methodology for modeling the dependency of the device performances (i.e. Electrical Parameters-EPs) with the influential technology parameters (i.e. Process Control Monitor parameters-PCMs), at an early stage (pre-Silicon). Using a set of standard Monte Carlo co-simulations of PCM structures and the circuit schematics (to maintain consistent process variation), it employs a feature selection step to choose the influential PCMs and it trains a Machine Learning regression algorithm. Both are wrapped up in a Bayesian Optimization framework to find the optimal feature set and the regression hyperparameters. The obtained regression model can explain the functional dependency of the EP on the influential PCMs. Thus, it directly enables sensitivity analysis to process variation and parametric yield prediction of the integrated circuit, as it will be illustrated for the case of an experimental Infineon Technologies product.
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IEEE Transactions on Circuits and Systems I: Regular Papers, 2009
Using the behavioral model of a circuit to perform behavioral Monte Carlo simulation (BMCS) is a fast approach to estimate performance shift under process variation with detailed circuit responses. However, accurate Monte Carlo analysis results are difficult to obtain if the behavioral model is not accurate enough. Therefore, this paper proposes to use an efficient bottom-up approach to generate accurate process-variation-aware behavioral models of CPPLL circuits. Without blind regressions, only one input pattern in the extraction mode sufficiently obtains all required parameters in the behavioral model. A quasi-SA approach is also proposed to accurately reflect process variation effects. Considering generic circuit behaviors, the quasi-SA approach saves considerable simulation time for complicated curve fitting but still keeps estimation accuracy. The experimental results demonstrate that the proposed bottom-up modeling flow and quasi-SA equations provide similar accuracy as in the RSM approach, using less extraction cost as in the traditional sensitivity analysis approach.
The 17th Annual SEMI/IEEE ASMC 2006 Conference
To increase the flexibility of existing production control algorithms and reduce the variation and mean of fabricator cycle times, a Fluctuation Smoothing for the Variation of Cycle Time (FSVCT) policy was implemented at IBM's 200mm semiconductor wafer fabrication facility. Extensions allowing for products with different cycle times and enabling the change of cycle time targets during production were developed. The policy was named the Multi-Flow Production Index (MFPx), reflective of its capabilities. Increased production agility and a controlled variation of cycle time resulted from the implementation.
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Assessing IC manufacturing process fluctuations and their impacts on IC interconnect performance has become unavoidable for modern DSM designs. However, the construction of parametric interconnect models is often hampered by the rapid increase in computational cost and model complexity. In this paper we present an efficient yet accurate parametric model order reduction algorithm for addressing the variability of IC interconnect performance. The efficiency of the approach lies in a novel combination of low-rank matrix approximation and multi-parameter moment matching. The complexity of the proposed parametric model order reduction is as low as that of a standard Krylov subspace method when applied to a nominal system. Under the projection-based framework, our algorithm also preserves the passivity of the resulting parametric models.
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Process-induced variations are an important consideration in the design of integrated circuits. Until recently, it was sufficient to model die-to-die shifts in device performance, leading to the well known worst-case modeling and design methodology . However, current and near-future integrated circuits are large enough that device and interconnect parameter variations within the chip are as important as those same variations from chip to chip. This presents a new set of challenges for process modeling and characterization and for the associated design tools and methodologies.
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IEEE Transactions on Semiconductor Manufacturing, 2000
Process-induced variability has become a predominant limiter of performance and yield of IC products especially in a deep submicron technology. However, it is difficult to accurately model systematic process variability due to the complicated and interrelated nature of physical mechanisms of variation. In this paper, a simple and practical method is presented to decompose process variability using statistics of the measurements from manufacturing inline test structures without assuming any underlying model for process variation. The decomposition method utilizes a variant of principal component analysis and is able to reveal systematic variation signatures existing on a die-to-die and wafer-to-wafer scale individually. Experimental results show that the most dominant die-to-die variation and wafer-to-wafer variation represent 31% and 25% of the total variance of a large set of manufacturing inline parameters in 65-nm SOI CMOS technology. The process variation in RF circuit performance is also analyzed and shown to contain 66% of process variation obtained with manufacturing inline parameters.
Models of Process Variations in Device and Interconnect
Design of High-Performance Microprocessor Circuits, 2000
Introduction: Sources of Variation Variation is the deviation from intended or designed values for a structure or circuit parameter of concern. The electrical performance of microprocessors or other integrated circuits are impacted by t wo sources of variation. Environmental factors are those which arise during the operation of a circuit, and include variations in power supply, switching activity, and temperature of the chip or across the chip. Physical factors during manufacture result in structural device and interconnect variations which a r e essentially permanent. These variations arise due to processing and masking limitations, and result in random or spatially varying deviations from designed parameter values. in this chapter we will focus on parametric variation due to continuously varying structural or electrical parameters, as these can signi cantly impact not only yield but also performance in high speed microprocessor and other digital circuits. Such parametric variation is becoming a larger concern, as variation and margins for device and
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In this paper, we introduce a new modified version of the scheduling approach, Control Point Policy (CPP) for semiconductor wafer fabrication lines and compare its performance with the popular Earliest Due Date (EDD), Minimum Slack (MS) and Critical Ratio (CR) scheduling policies. Discrete event modeling and simulations are created to evaluate the performance of CPP for three important performance measures; cycle times, waiting times and inventory levels. New insights for system performance are developed with the implementation of CPP at bottleneck stations and the introduction of finite size buffers between all the workstations. Our simulation results demonstrate the ability of CPP to achieve lowest cycle times with minimum inventory levels for situations where products with similar process characteristics are prioritized over each other. Our simulation experiments show that the CPP generates good system performance for environments where multiple products at different processing stages compete for limited resources.
Implementation of a Fluctuation Smoothing Production Control Policy in IBM’s 200mm Wafer Fab
Conference on Decision and Control, 2005
Efficient operation of IBM Vermont’s 200mm semiconductor wafer fabrication facility is essential to achieve the objective of transforming the site into a world class foundry manufacturer. To that end, we develop a fluctuation smoothing for the variation of cycle time (FSVCT) production control policy capable of allowing for a diversity of cycle time commitments. The policy directs which lot should