A Perspective Review of Tunnel Field Effect Transistor with Steeper Switching Behavior and Low off Current (I OFF ) for Ultra Low Power Applications (original) (raw)
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IOP Publishing, 2020
In this research work, a n-type silicon tunneling field effect transistor (TFET) has been designed and investigation has been carried out on its performances by altering different device parameters such as gate insulator dielectric constant, channel thickness, gate geometry, and channel length. The performances have been evaluated based on subthreshold swing, threshold voltage and Ion/I of f ratio of the devices. The goal is to find a device which would simultaneously have a low subthreshold swing (SS), low threshold voltage, and a high Ion/I of f ratio. It has been observed that having a double gate, short channel length, high-κ dielectric, and low channel thickness leads us towards a compact design and the device exhibits very promising values of the aforementioned performance criteria. The most attractive proposition about a TFET is its ability to have a subthreshold swing lower than 60 mV/dec which is the theoretical limit of a MOSFET. In this study, an optimized device is obtained which has a subthreshold swing (point) of around 26 mV/dec and an Ion/I of f ratio in the order of 10 13. In addition, an inverter has been designed using a n-type TFET and a resistor to show the potential of TFETs to be used in logic circuits.
Journal of Physics: Conference Series, 2020
In this research work, a n-type silicon tunneling field effect transistor (TFET) has been designed and investigation has been carried out on its performances by altering different device parameters such as gate insulator dielectric constant, channel thickness, gate geometry, and channel length. The performances have been evaluated based on subthreshold swing, threshold voltage and I on /I off ratio of the devices. The goal is to find a device which would simultaneously have a low subthreshold swing (SS), low threshold voltage, and a high I on /I off ratio. It has been observed that having a double gate, short channel length, high-k dielectric, and low channel thickness leads us towards a compact design and the device exhibits very promising values of the aforementioned performance criteria. The most attractive proposition about a TFET is its ability to have a subthreshold swing lower than 60 mV/dec which is the theoretical limit of a MOSFET. In this study, an optimized device is obt...
Leakage-reduction design concepts for low-power vertical tunneling field-effect transistors
2010
Abstract Using an atomistic full-band quantum transport solver, we investigate the performances of vertical band-to-band tunneling FETs (TFETs) whose operation is based on the enhancement of the gate-induced drain leakage mechanism of MOSFETs, and we compare them to lateral pin devices. Although the vertical TFETs offer larger tunneling areas and therefore larger on currents than their lateral counterparts, they suffer from lateral source-to-drain tunneling leakage away from the gate contact.
Ultra Low Power Circuit Design Using Tunnel FETs
2012 IEEE Computer Society Annual Symposium on VLSI, 2012
The proliferation of ubiquitous and mobile computing systems has created a new segment in the design space where energy efficiency is the most critical design parameter. With the end user expecting more functionality from these types of systems, there is a pressing need to evaluate emerging technologies that can overcome the limitations of CMOS. This work evaluates the potential of one such prospective MOSFET replacement device-the Tunnel FET (TFET). Novel circuit designs are presented to overcome unique design challenges posed by TFETs. The impacts of the proposed design techniques are characterized and a sparse prefix tree adder employing the proposed designs is presented. A considerable improvement in delay and significant reduction in energy is observed due to the combined impact of circuit and technology co-exploration.
2009 IEEE International Electron Devices Meeting (IEDM), 2009
Vertical In 0.53 Ga 0.47 As tunnel field effect transistors (TFETs) with 100nm channel length and highk/metal gate stack are demonstrated with high I on /I off ratio (>10 4 ). At V DS = 0.75V, a record on-current of 20µA/µm is achieved due to higher tunneling rate in narrow tunnel gap In 0.53 Ga 0.47 As. The TFETs exhibit gate bias dependent NDR characteristics at room temperature under forward bias confirming band to band tunneling. The measured data are in excellent agreement with two-dimensional numerical simulation at all drain biases. A novel 6T TFET SRAM cell using virtual ground assist is demonstrated despite the asymmetric source/drain configuration of TFETs. Introduction: Inter-band tunnel FETs (TFETs) with a gatemodulated Zener tunnel junction at the source are of interest for MOSFET replacement since the reverse biased tunnel junction in the former eliminates the high-energy tail of the Fermi distribution of valence band electrons in the source region thereby allowing for abrupt turn-on near the OFF state 1 . However, till date, almost all Si and Si x Ge 1-x based TFETs exhibit low I on due to high tunnel barrier. We present here improved I on and I on -I off ratios utilizing a vertical In 0.53 Ga 0.47 As TFET. A fundamental advantage of the vertical transistor design is that high quality, in-situ doped junctions are realized enabling not only observation of room temperature NDR effects but also reduction of off-state reverse biased p+/i/n+ leakage. Device Fabrication: N-channel In 0.53 Ga 0.47 As TFETs were fabricated using MBE grown epitaxial structure on semiinsulating InP substrate. The epitaxial layers comprise of 300nm thick n+ drain region (Si doping of 5x10 19 cm -3 ), 100nm intrinsic channel region and 60nm thick p+ source region (C doping of 1x10 20 cm -3 ) . After source metal (Ti/Pt/Au) evaporation and lift-off, a facet dependent mesa sidewall etch is performed using citric acid and peroxide chemistry exposing the n+ region . A highly conformal 10nm thick Al 2 O 3 is deposited on the mesa sidewall using atomic layer deposition (ALD) followed by gate metallization (Pt/Au) and liftoff . A subsequent lithography step defines source/drain contact openings and the Al 2 O 3 film is removed thereof to make direct contact to the source/drain regions, followed by a final isolation etch . Figs. 1g-h show the SEM images of fabricated In 0.53 Ga 0.47 As vertical TFET featuring gate air-bridge and conformal gate stack on the sidewall. Device Results and Discussion: show the measured transfer and output characteristics of the 100nm channel length tunnel transistors at room temperature. The minimum current ("leakage floor") at V DS = 50mV is only 40 pA/µm increasing to 6nA/µm at V DS = 0.75V. The corresponding on currents are 0.5µA/µm (linear) and 20µA/µm (saturation). This translates to I on -I off ratio of ~ 10
Design and Analysis of Tunnel FET for Low Power High Performance Applications
International Journal of Modern Education and Computer Science, 2018
Tunnel FET is a promising device to replace MOSFET in low power high performance applications. This paper highlights and compares the best TFET designs proposed in the literature namely: Double gate Si-based TFET, InAs TFET device and III-V semiconductor (GaAs 1-x Sb x-InAs) based TFET device. Simulations are performed using TCAD tool and simulation results suggest that conventional DGTFET device has less on current and degraded subthreshold slope as compared to InAs and III-V semiconductor based TFET device. InAs based TFET device provides steep subthreshold slope of 61 mV/dec and off current of the order of nano-amperes at sub 1V operation thereby making it an ideal choice for low power high performance applications. The variation in the performance of the III-V HTFET device with the variation in the mole fraction is also studied in detail. Carefully choosing the mole fraction value in III-V semiconductor based HTFET device can lead to better device performance.
Complementary tunneling transistor for low power application
Solid-State Electronics, 2004
The metal oxide semiconductor field effect transistor (MOSFET) is scaling to a ''tunneling epoch'', in which multiple leakage current induced by different tunneling effects exist. The complementary Si-based tunneling transistors are presented in this paper. The working principle of this device is investigated in detail. It is found that the band-to-band tunneling current is be controlled by the gate-to-source voltage. Due to the reverse biased p-i-n diode structure, an ultra-low leakage current is achieved. The sub-threshold swing of TFET is not limited by kt/q, which is the physical limit of the MOSFET. Using the CMOS compatible processes, the complementary TFETs (CTFET) are fabricated on one wafer. From a circuit point of view, the compatibility between TFET and MOSFET enables the transfer of CMOS circuits to CTFET circuits.
Subthreshold-swing physics of tunnel field-effect transistors
AIP Advances, 2014
Band-to-band tunnel field-effect-transistors (TFETs) are considered a possible replacement for the conventional metal-oxide-semiconductor field-effect transistors due to their ability to achieve subthreshold swing (SS) below 60 mV/decade. This letter reports a comprehensive study of the SS of TFETs by examining the effects of electrostatics and material parameters of TFETs on their SS through a physics based analytical model. Based on the analysis, an intrinsic SS degradation effect in TFETs is uncovered. Meanwhile, it is also shown that designing a strong onset condition, quantified by an introduced concept - “onset strength”, for TFETs can effectively overcome this degradation at the onset stage, and thereby achieve ultra-sharp switching characteristics. The uncovered physics provides theoretical support to recent experimental results, and forward looking insight into more advanced TFET design.
Impact of the RT‐level architecture on the power performance of tunnel transistor circuits
International Journal of Circuit Theory and Applications, 2017
SummaryTunnel field‐effect transistors (TFETs) are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of Complementary Metal Oxide Semiconductor (CMOS) technology. In this paper, we analyze the relationship between devices and register transfer–level architecture choices. We claim that architectural issues should be considered when evaluating this type of transistors because of the differences in delay versus supply voltage behavior exhibited by TFET logic gates with respect to CMOS gates. More specifically, the potential of pipelining and parallelism, both of which rely on lowering supply voltage, as power reduction techniques is evaluated and compared for CMOS and TFET technologies. The results obtained show significantly larger savings in power and energy per clock cycle for the TFET designs than for their CMOS counterparts, especially at low voltages. Pipelining a...