Modeling the effect of technology trends on the soft error rate of combinational logic (original) (raw)

Modeling the Impact of Device and Pipeline Scaling on the Soft Error Rate of Processor Elements

2002

This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to-end model that enables us to compute the soft error rates (SER) for existing and future microprocessor-style designs. The model captures the effects of two important masking phenomena, electrical masking and latching-window masking, which inhibit soft errors in combinational logic. We quantify the SER due to high-energy neutrons in SRAM cells, latches, and logic circuits for feature sizes from 600nm to 50nm and clock periods from 16 to 6 fan-out-of-4 inverter delays. Our model predicts that the SER per chip of logic circuits will increase nine orders of magnitude from 1992 to 2011 and at that point will be comparable to the SER per chip of unprotected memory elements. Our result emphasizes that computer system designers must address the risks of soft errors in logic circuits for future designs.

Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits

IEEE Transactions on Dependable and Secure Computing, 2009

Radiation-induced soft errors in combinational logic is expected to become as important as directly induced errors on state elements. Consequently, it has become important to develop techniques to quickly and accurately predict soft-error rates (SERs) in combinational circuits. In this work, we present methodologies to model soft errors in both the device and logic levels. At the device level, a hierarchical methodology to model neutron-induced soft errors is proposed. This model is used to create a transient current library, which will be useful for circuit-level soft-error estimation. The library contains the transient current response to various different factors such as ion energies, operating voltage, substrate bias, angle, and location of impact. At the logic level, we propose a new approach to estimating the SER of logic circuits that attempts to capture electrical, logic, and latch window masking concurrently. The average error of the SER estimates using our approach, compared to the estimates obtained using circuit-level simulations, is 6.5 percent while providing an average speedup of 15,000. We have demonstrated the scalability of our approach using designs from the ISCAS-85 benchmarks.

Logic soft errors in sub-65nm technologies design and CAD challenges

2005

Logic soft errors are radiation induced transient errors in sequential elements (flip-flops and latches) and combinational logic. Robust enterprise platforms in sub-65nm technologies require designs with built-in logic soft error protection. Effective logic soft error protection requires solutions to the following three problems: (1) Accurate soft error rate estimation for combinational logic networks;

Low Cost Circuit-Level Soft Error Mitigation Techniques for Combinational Logic

Scientia Iranica, 2015

Following technology scaling trend, CMOS circuits are facing more reliability challenges such as soft errors caused by radiation. Soft error protection imposes some design overheads in power consumption, area, and performance. In this article, we propose a low cost and highly e ective circuit to lter out the e ect of particle strikes in combinational logic. This circuit will result in decreasing Soft Error Propagation Probability (SEPP) in combinational logic. In addition, we propose a novel transistor sizing technique that reduces cost-eciently Soft Error Occurrence Rate (SEOR) in the combinational logic. This technique generally results in lower design overhead as compared with previous similar techniques. In the simulations run on di erent ISCAS'89 circuit benchmarks, combining the proposed techniques, we achieved up to 70% SER reduction in the overall soft error rate of the circuits for a certain allowed overhead budget.

On the role of timing masking in reliable logic circuit design

2008

Abstract Soft errors, once only of concern in memories, are beginning to affect logic as well. Determining the soft error rate (SER) of a combinational circuit involves three main masking mechanisms: logic, timing and electrical. Most previous papers focus on logic and electrical masking. Here, we develop static and statistical analysis techniques to estimate timing masking through the error-latching window of each gate.

A highly-efficient technique for reducing soft errors in static CMOS circuits

IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings.

Soft errors are functional failures resulting from the latching of single-event transients (transient voltage fluctuations at a logic node or SETs) caused by high-energy particle strikes or electrical noise. Traditionally, they have been deemed to be a problem in memory structures, for which effective techniques (such as error correcting codes) are well known. However, due to technology scaling and reduced supply voltages, they are expected to increase by several orders of magnitude in logic circuits. Existing circuit and architectural approaches to addressing soft errors in logic circuits have appreciable area/cost, performance, and/or energy overheads or are limited to particular types of circuits (combinational or sequential). We present a very efficient and systematic error masking technique that uses the same circuitry to cope with soft errors in combinational and sequential circuits. It prevents an SET pulse of width less than approximately half of the slack available in the propagation path from latching and turning into a soft error. The SET is masked without additional delay and within the clock cycle time in an area-and energy-efficient manner, which makes this technique attractive for commodity as well as reliabilitycritical applications. Our technique also tolerates soft errors in the overhead circuitry, which we minimize through clustering. Application of our technique to ISCAS85 benchmark circuits yields an average SER reduction of 70.93% with an average area overhead of only 11.98%.

Soft Error Rate Analysis for Combinational Logic Using an Accurate Electrical Masking Model

IEEE Transactions on Dependable and Secure Computing, 2011

Accurate electrical masking modeling represents a significant challenge in soft error rate analysis for combinational logic circuits. In this paper, we use table lookup MOSFET models to accurately capture the nonlinear properties of submicron MOS transistors. Based on these models, we propose and validate the transient pulse generation model and propagation model for soft error rate analysis. The pulse generated by our pulse generation model matches well with that of HSPICE simulation, and the pulse propagation model provides nearly one order of magnitude improvement in accuracy over the previous models. Using these two models, we propose an accurate and efficient block-based soft error rate analysis method for combinational logic circuits.

Joint Soft-Error-Rate (SER) Estimation for Combinational Logic and Sequential Elements

IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016

With drastic device shrinking, low operating voltages , increasing complexities, and high speed operations, radiation-induced soft errors have posed an ever increasing reliability challenge to both combinational and sequential circuits in advanced CMOS technologies. Therefore, it is imperative to devise efficient soft error rate (SER) estimation methods, in order to evaluate the soft error vulnerabilities for cost-effective robust circuit design. Previous works either analyze only SER in combinational circuits or evaluate soft error vulnerabilities in sequential elements. In this paper, a joint SER estimation framework is proposed, which considers single-event transients (SETs) in combinational logic and multiple cell upsets (MCUs) in sequential components. Various masking effects are considered in the combinational SER estimation process, and several typical radiation-hardened and non-hardened flip-flop structures are analyzed and compared as the sequential elements. A schematic and layout co-simulation approach is proposed to model the MCUs for redundant sequential storage structures. Experimental results of a variety of ISCAS benchmark circuits using the Nangate 45nm CMOS standard cell library demonstrate the difference in soft error resilience among designs using different sequential elements and the importance of modeling MCUs in redundant structures. Keywords—Soft error, hardened flip-flop, single-event upset, multiple cell upset.

Analysis of soft error rate in flip-flops and scannable latches

IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings., 2000

Abstracr-Sofi the critical charge hy increasing the gate capacitance while errors are gaining importance as technology scales. Flip-flops, an important component of pipelined architectures, are becoming more susceptible to soft errors. This work analyzes soft error rates on a variety of flip-flops. The analysis was performed hy implementing and simulating the various designs in 70 nm, 1V CMOS technology. First, we evaluate the critical charge for the snsceptihle nodes in each design. Further, we implement two hardening techniques and present the results. One attempts to increase the other improves the overall robustness of the circuit by replicating the master stage of the master slave nip-flops, which leads to reduced power and area overhead. 0-7803-8182-3/03/$17.00 02003 IEEE