Ultra low power wide range four quadrant analog multiplier (original) (raw)

Compact, Low-Voltage, Low-Power and High Bandwidth CMOS Four-Quadrant Analog Multiplier

In this paper, a new compact, low power and low voltage structure for CMOS analog multiplier is proposed. All of them are implemented using a compact circuit. The circuit is designed and analyzed in 0.18µm CMOS process model. Simulation results for the circuit with a 1.2V single supply show that it consumes only 25µw quiescent power with 2GHz bandwidth and 1.5% THD.

CMOS implementation for low power analog multiplier

THE 2ND UNIVERSITAS LAMPUNG INTERNATIONAL CONFERENCE ON SCIENCE, TECHNOLOGY, AND ENVIRONMENT (ULICoSTE) 2021

A novel CMOS four quadrant Analog multiplier in voltage mode configuration is designed and simulation. The results are analyzed using CMOS 180nm technology. The input voltage is applied to bulk terminal MOS to make it operate in exponential manner. The proposed multiplier architecture uses this exponential circuit and provides high performance characteristics for the Multiplier circuit. The results aresimulated on 180 nm technology. The 3dB measured bandwidth is 200.33MHz, power consumption achieved is 598nW. The designed multiplier architecture is feasible for many applications because of low voltage, low power high bandwidth and simple structure.

A novel current-mode very low power analog cmos four quadrant multiplier

Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005., 2005

In this paper, a novel current mode CMOS four-quadrant analog multiplier circuit is presented. The multiplication is implemented by four translinear loops with MOS transistors operating in weak inversion. Information carrying signals are differential balanced currents. The multiplier circuit has been implemented in a test chip in a standard 0.35 m CMOS technology. The experimental measurements (dc bias current of 250 nA and a power supply of 2.0 V) show a bandwidth of 200 kHz and a THD figure value lower than 0.9 %. The multiplier features a wide signal dynamic range and linearity, low power consumption (the maximum power consumption is of 5.5·10 -6 W) and very low area (18.7 10 -3 mm 2 ). The multiplier is suitable for a wide range of analog signal processing applications. Due to the low power and silicon area consumption, scalability and modularity can be also easily integrated in massive parallel systems.

FGMOS four-quadrant analog multiplier

2012 9th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE), 2012

A novel four-quadrant analog multiplier using floating gate MOS (FGMOS) transistors operating in the saturation region is presented. The drain current is proportional to the square of the weighted sum of the input signals. This square law characteristic of the FGMOS transistor is used to implement the quarter square identity by utilizing only six FGMOS transistors. The main features of this remarkably simple multiplier circuit configuration are the large input signal range equal to 100% of the supply voltage, nonlinearity of 0.0081%, bandwidth of 1.4-1.5 Ghz and THD of maximum 2.67% (while the inputs are at their maximum values).

Wideband and Low Power CMOS Analog Multiplier in Deep Submicron Technology.

International Journal of Engineering Sciences & Research Technology, 2014

In this paper CMOS Four Quadrant Analog Multiplier is designed. It is based on pair of common source amplifier, which acts as input transistor and two identical voltage controlled square root blocks which operate as nonlinear cancellation path. Simulated results using eldo spice in Mentor Graphics Tools for 350nm and 180nm CMOS technology. The main performances of the multiplier including bandwidth, power dissipation, and gain are improved. In this paper CMOS Four Quadrant Analog Multiplier is designed. It is based on pair of common source amplifier, which acts as input transistor and two identical voltage controlled square root blocks which operate as nonlinear cancellation path. Simulated results using eldo spice in Mentor Graphics Tools for 350nm and 180nm CMOS technology. The main performances of the multiplier including bandwidth, power dissipation, and gain are improved. In this paper CMOS Four Quadrant Analog Multiplier is designed. It is based on pair of common source amplifier, which acts as input transistor and two identical voltage controlled square root blocks which operate as nonlinear cancellation path. Simulated results using eldo spice in Mentor Graphics Tools for 350nm and 180nm CMOS technology. The main performances of the multiplier including bandwidth, power dissipation, and gain are improved. In this paper CMOS Four Quadrant Analog Multiplier is designed. It is based on pair of common source amplifier, which acts as input transistor and two identical voltage controlled square root blocks which operate as nonlinear cancellation path. Simulated results using eldo spice in Mentor Graphics Tools for 350nm and 180nm CMOS technology. The main performances of the multiplier including bandwidth, power dissipation, and gain are improved. In this paper CMOS Four Quadrant Analog Multiplier is designed. It is based on pair of common source amplifier, which acts as input transistor and two identical voltage controlled square root blocks which operate as nonlinear cancellation path. Simulated results using eldo spice in Mentor Graphics Tools for 350nm and 180nm CMOS technology. The main performances of the multiplier including bandwidth, power dissipation, and gain are improved.

A 1.2V Single Supply and Low Power, CMOS Four Quadrant Analog Multiplier

In this paper, a new low voltage topology for analog multiplier is presented. The circuit can be used with single lowpower supply. The complete circuit has only twelve transistors; therefore, it satisfies the need for compact sub-circuit in analog VLSI systems. The mathematical discussion on the power consumption, total harmonic distortion and other features of the circuit and also simulation results in 0.18µm CMOS technology are presented. The results show 113µW power consumption with 1.2V single supply, 1.1% total harmonic distortion (THD) and 1GHz band-width.

A new high speed and low power four-quadrant CMOS analog multiplier in current mode

AEU - International Journal of Electronics and Communications, 2009

In this paper a new CMOS current-mode four-quadrant analog multiplier and divider circuit based on squarer circuit is proposed. The dual translinear loop is the basic building block in realization scheme. Supply voltage is 3.3 V. The major advantages of this multiplier are high speed, low power, high linearity and less dc offset error. The circuit is designed and simulated using HSPICE simulator by level 49 parameters (BSIM3v3) in 0.35 m standard CMOS technology. The simulation results of analog multiplier demonstrate a linearity error of 1.1%, a THD of 0.97% in 1 MHz, a −3 dB bandwidth of 41.8 MHz and a maximum power consumption of 0.34 mW.

Four quadrant FGMOS analog multiplier

2011

A novel four-quadrant analog multiplier using floating gate MOS (FGMOS) transistors operating in the saturation region is presented. The drain current is proportional to the square of the weighted sum of the input signals. This square law characteristic of the FGMOS transistor is used to implement the quarter square identity by utilizing only six FGMOS transistors. The main features of this remarkably simple multiplier circuit configuration are the large input signal range equal to 100% of the supply voltage, nonlinearity of 0.0081%, bandwidth of 1.4--1.5 Ghz and THD of maximum 2.67% (while the inputs are at their maximum values).

A High-Speed High-Input Range Four Quadrant Analog Multiplier

Majlesi Journal of Electrical Engineering, 2010

In this paper, a CMOS four quadrant multiplier based on flipped voltage follower and differential squaring circuit is presented. The proposed circuit has a compact architecture which operates at a higher speed and a higher input voltage range compared to the previously presented structures. The transistors operate in both saturation and ohmic regions. The circuit operates with a single supply voltage of 3.3V in a 0.35 µm CMOS technology where the total harmonic distortion (THD) is less than 1.1%, the linearity error is also less than 3%,-3db frequency is more than 180 MHz and the voltage input range is 3 p p V −. Simulation results are given to verify the functionality of the proposed multiplier.

Compact low-voltage CMOS four-quadrant analogue multiplier

Electronics Letters, 2006

A compact architecture for a four-quadrant analogue multiplier circuit is presented. The circuit is formed by connecting common source amplifiers with a pair of differential flipped voltage followers. This results in a novel cancellation of the nonlinear terms in the subcurrents, leading to the desired four-quadrant analogue multiplier. The circuit combines low complexity with low-voltage operation and low static power consumption. Simulated results using a 0.35 mm CMOS process are provided.