Towards Power Centric Analog Design (original) (raw)
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Power consumption of analog circuits: a tutorial
Analog Integrated Circuits and Signal Processing, 2010
A systematic approach to the power consumption of analog circuits is presented. The power consumption is related to basic circuit requirements, as dynamic range, bandwidth, noise figure and sampling speed and is considering basic device and device scaling behavior. Several kinds of circuits are treated, as samplers, amplifiers, filters and oscillators. The objective is to derive lower bounds to power consumption in analog circuits, to be used as design targets when designing power-constrained analog systems. Keywords Low power design • fundamental limits • dynamic range • technology scaling • analog building blocks
2006 IEEE Workshop on Signal Processing Systems Design and Implementation, 2006
Wireless Sensor Network (WSN) nodes require components with ultra-low power consumption, as they must operate without an external power supply. One technique for reducing consumption of a system is to scale it to a smaller technology; however, in recent technologies is not clear whether the decrease in dynamic power consumption outweighs the increase in static power consumption (due to leakage currents). Here this is considered by examining the power consumption of three implementations of an analog to digital converter (ADC). One in 350 nm, one in 180 nm, and one in 90 nm, were simulated and compared. The results show that the dynamic power consumption was reduced by a factor of four over the three technologies, but standby power consumption increased by an order of magnitude. The power consumption of the 180 nm implementation was always lower than the 350 nm implementation. However, assuming a WSN application with a duty cycle of 1%, the effective power consumption of the 90 nm ADC was higher than both the 180 nm and the 350 nm implementation. This highlights the dominance of leakage current in determining the effective power consumption in lowthroughput nodes.
High Level Power Estimation and Reduction Techniques for Power Aware Hardware Design
2010
for their mentorship, guidance and help. I would like to acknowledge the support received from Cebatech Inc., NSF-CRCD, NSF CAREER grants, which provided funding for the work reported in this dissertation. Special thanks are due to my friends Luv Kothari and Deepak Mathaikutty for motivating and guiding me during the course of PhD. To Wei Zhang for numerous hours of technical discussions and guidance during my PhD, and for being patient and supportive through those discussions. To Gaurav Singh and Avinash Lakshminarayana for helping and discussing many research topics related to this thesis.
Solid-State Circuits, …, 1992
Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining coniputational throughput. Techniques for low-power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. An architectural-based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations. This optimum is achieved by trading increased silicon area for reduced power consumption.
Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies
IEEE Transactions on Very Large Scale Integration Systems, 2002
This paper describes methods for analog-power estimation and practically applies them to two different classes of analog circuits. Such power estimators, that return a power estimate given only a block's specification values without knowing its detailed circuit implementation, are valuable components for architectural exploration tools and hence interesting for high-level system designers. As an illustration, two estimators are presented: one for high-speed analog-to-digital converters (ADCs) and one for analog-continuous time filters. The ADC power estimator is a technology scalable closed formula and yields first-order results within an accuracy factor of about 2.2 for the whole class of high-speed Nyquist-rate ADCs. The filter-power estimator is of a more complex nature. It uses a crude filter synthesis, in combination with operational transconductor amplifier behavioral models to generate accurate results as well, but restricted to certain filter implementations.
Design principles for low-voltage low-power analog integrated circuits
Analog Integrated Circuits and Signal Processing, 1995
In this paper it is argued that there are good reasons to choose current as the information-carrying quantity in the case of low-voltage low-power design constraints. This paper focuses on the influence of the transfer quality on that choice. To obtain power-efficient transfer quality, indirect feedback is shown to be a good alternative to traditional feedback techniques.
Low power design for DSP: methodologies and techniques
Microelectronics Journal, 1996
Power dissipation is becoming a limiting factor in the realization of VLSI systems. The principal reasons for this are maximum operating temperature and, for portable applications, battery life. Because of the relatively greater complexity, the power dissipation in digital signal processing (DSP) applications is of special significance, and low power design technique,'; are now emerging. This paper provides an overview of the techniques and methodologies that have emerged in the past few years for DSP system design. These include techniques for minimizing power at architectural ~.nd algorithmic levels including DSP programming issues. In addition, the paper indicates some potential design directions.
Ultra-Low-Voltage Design of Energy-Efficient Digital Circuits
Analog Circuits and Signal Processing, 2015
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