A systematic investigation of the integrated effects of gate underlapping, dual work functionality and hetero gate dielectric for improved performance of CP TFETs (original) (raw)
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A Novel Approach to Improve the Performance of Charge Plasma Tunnel Field-Effect Transistor
IEEE Transactions on Electron Devices, 2018
A distinct approach is presented for realizing charge plasma tunnel field-effect transistor (CP TFET) wherein p + substrate is taken as silicon film and then metal electrodes with specific work functions are deposited over the silicon film to accumulate n + drain and intrinsic channel regions. This creates abruptness and reduces the barrier at the source/channel interface of CP TFET, which improves the dc characteristics of the device. Furthermore, the drain electrode is separated into two sections and applied with dual work function, which reduces the ambipolar behavior, parasitic capacitance, and enhances radio frequency parameters. The crux of the script is to advance the performance of the device while maintaining the classical CMOS fabrication flow with its inherent advantages by using p + substrate initially. To analyze the performance, a comparison between conventional CP TFET and dual drain electrode CP TFET (proposed) is shown at the simulation level. Optimization of length and workfunction of the section of drain electrode adjacent to the channel is demonstrated to assess the desired ON-current and ambipolarity of the device. Furthermore, the device performance is examined with the application of multigate work function and heterogate dielectric engineering to achieve more improvements in device performance.
Superlattices and Microstructures, 2020
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Performance investigation of hetero material (InAs/Si)‐based charge plasma TFET
Micro & Nano Letters, 2017
The charge plasma-based tunnel field-effect transistor (TFET) has been seen as the potential candidate to replace the conventional TFET as it offers fabrication simplicity and its proficiency to be used for ultra-low-power applications. A charge plasma TFET (CPTFET) with hetero materials for enhancement of device performance is presented. For this, a narrow bandgap material (InAs) is used instead of silicon in source region for reducing the lateral tunnelling distance at the source/channel interface. The reduced tunnelling width at the source/ channel junction enables higher band-to-band tunnelling generation rate, thus the device offers higher ON-state current. In this context, a comparative study of CPTFET and hetero junction charge plasma TFET (H-CPTFET) has been performed in terms of transfer characteristic (I ds-V gs), transconductance (g m), gate-to-drain capacitance (C gd), cutoff frequency (f T) and gain-bandwidth product. In addition to this, the effect of variation in channel length (L g) and drain to source voltage (V ds) on the DC and analogue/radio frequency performance of H-CPTFET is also analysed.
Micro & Nano Letters, 2018
Abruptness at tunnelling junction is a vital issue with doped tunnel field-effect transistor (TFET) to achieve improved electrostatic characteristics. This task is more problematic for charge plasma TFET (CP-TFET) because of large tunnelling barrier at the channel/source interface. In this regard, an effective approach has already been employed through implantation of a horizontal metallic splint (HMS) inside the dielectric region near channel/source joint for improved electrical behaviour of CP-TFET. However, placement of a vertical metal splint (VMS) provides contact for HMS and gate electrode, which gives magnificent analogue/DC characteristics for newer structure. Combination of HMS and VMS (i.e. double metal splint (DMS)) increases electron density at channel/source junction for improved electron tunnelling rate compared with only HMS structure. In this regard, a complete comparative analysis of DMS CP TFET (DMS-CP-TFET) is performed between CP-TFET and HMS-CP-TFET. Furthermore, consequence of length and work-function variation of DMS and HMS on DC/RF parameters is investigated in device optimisation part of this work.
Characterization of silicon tunnel field effect transistor based on charge plasma
Indonesian Journal of Electrical Engineering and Computer Science
The aim of the proposed paper is an analytical model and realization of the characteristics for tunnel field-effect transistor (TFET) based on charge plasma (CP). One of the most applications of the TFET device which operates based on CP technique is the biosensor. CP-TFET is to be used as an effective device to detect the uncharged molecules of the bio-sample solution. Charge plasma is one of some techniques that recently invited to induce charge carriers inside the devices. In this proposed paper we use a high work function in the source (ϕ=5.93 eV) to induce hole charges and we use a lower work function in drain (ϕ=3.90 eV) to induce electron charges. Many electrical characterizations in this paper are considered to study the performance of this device like a current drain (ID) versus voltage gate (Vgs), ION/IOFF ratio, threshold voltage (VT) transconductance (gm), and sub-threshold swing (SS). The signification of this paper comes into view enhancement the performance of the dev...
This paper discusses the ambipolar behavior and proposes the ambipolar reduction techniques for charge plasma TFET devices. These techniques are based on drain engineering such as use of different drain electrode work function, enlargement of the drain spacer length and increase of the drain electrode height. For the validation of results, these techniques are implemented on four different doping-less TFET structures. The ambipolar behavior can be controlled and removed by (1) using the drain electrode work function of 4.4 eV (2) doubling the drain spacer length (3) increasing the drain electrode height by more than three times, for the specified device dimensions. By using any of these technologies with specified value of design parameters, the ambipolar conduction can be completely removed without interrupting ON state and OFF state current.
Journal of Computational Electronics, 2019
A comparative investigation has been carried out on the charge plasma tunnel field-effect transistor (CP-TFET) and electrically doped TFET (ED-TFET). Both device structures are created on intrinsic silicon, but differ regarding the method employed to induce charge carriers in the intrinsic silicon area. In the charge plasma TFET, metal work function engineering is employed, while in the case of the ED-TFET, electrostatics is used to induce charge carriers at the drain/source side, resulting in the formation of n + drain and p + source regions. Both devices are analyzed for the same OFF-state current, which will reduce the gate leakage and enable a fair comparison of the devices. The analysis is carried out in terms of direct-current (DC) characteristics as well as analog and radiofrequency parameters, revealing that the charge plasma TFET exhibits better DC and analog/RF characteristics as compared with the electrically doped TFET. This occurs due to the lower work function applied at the source-channel region in the CP-TFET compared with the ED-TFET.
Applied Physics A, 2018
This article presents a new device configuration to enhance current drivability and suppress negative conduction (ambipolar conduction) with improved RF characteristics of physically doped TFET. Here, we used a new approach to get excellent electrical characteristics of hetero-dielectric short gate source electrode TFET (HD-SG SE-TFET) by depositing a metal electrode of 5.93 eV work function over the heavily doped source (P+) region. Deposition of metal electrode induces the plasma (thin layer) of holes under the Si/HfO 2 interface due to work function difference of metal and semiconductor. Plasma layer of holes is advantageous to increase abruptness as well as decrease the tunneling barrier at source/channel junction for attaining higher tunneling rate of charge carriers (i.e., electrons), which turns into 86.66 times higher ON-state current compared with the conventional physically doped TFET (C-TFET). Along with metal electrode deposition, gate electrode is under-lapped for inducing asymmetrical concentration of charge carriers in the channel region, which is helpful for widening the tunneling barrier width at the drain/channel interface. Consequently, HD-SG SE-TFET shows suppression of ambipolar behavior with reduction in gate-to-drain capacitance which is beneficial for improvement in RF performance. Furthermore, the effectiveness of hetero-gate dielectric concept has been used for improving the RF performance. Furthermore, reliability of C-TFET and proposed structures has been confirmed in term of linearity.
Applied Physics A, 2020
The hetero-gate dielectric (HGD) structure was recently experimentally demonstrated to enhance the electrical performance of tunnel field-effect transistors (TFETs). This study examined the mechanisms underlying the HGD structure functioning and investigated the design of the structure to enhance the electrical characteristics of TFETs with different ratios of lowand high-k equivalent oxide thicknesses (EOT). The on-current enhancement by the source-side dielectric heterojunction, which directly modulates the on-state tunnel width, was much larger than that by the drain-side dielectric heterojunction, which indirectly affects the on-current by modulating the subthreshold tunnel width. The subthreshold swing is improved by the formation of a conduction band well near the source-channel junction. However, the swing improvement is limited by the hump effect when this local potential well approaches the source. The optimal design of the HGD structure and the maximal enhancement of on-current considerably depend on the EOT ratio of low-and high-k dielectrics. The on-current is most enhanced by the optimized HGD structure at a low/high-k EOT ratio of ten times, that is, approximately 160% of the on-current of the uniform high-k TFET counterpart. Due to the continuous trend of increasing the k-values or scaling EOTs, understanding the dependence of device physics and design on the low/high-k EOT ratio is crucial to optimize the performance of HGD-TFETs.