A sub-1V dual-threshold domino circuit using product-of-sum logic (original) (raw)
2001, Proceedings of the 2001 international symposium on Low power electronics and design - ISLPED '01
A sub-1 V dual-threshold Domino circuit is proposed to accelerate the operation of CMOS digital circuits at below 1 V. The circuit combines a low and high thresholdvoltage (Vt) MOSFET with standby control to make it possible to achieve high-speed evaluation and low standby leakage current. A low-Vt foot nMOSFET is used to shorten precharge time and increase throughput. A product-of-sum logic form is used for implementation of a pull-down logic to increase the noise margin. An experimental 64-bit carrylook-ahead (CLA) adder demonstrated a 0.6-V operation with a standby power of 0.4 µW and a delay time of 4.8 ns.
Sign up for access to the world's latest research.
checkGet notified about relevant papers
checkSave papers to use in your research
checkJoin the discussion with peers
checkTrack your impact
Loading Preview
Sorry, preview is currently unavailable. You can download the paper by clicking the button above.