Deep Submicron CMOS Integrated Circuit Reliability Simulation with SPICE (original) (raw)

HiREV NEPP Technical Interchange: "CMOS Physics of Failure Lifetime Modeling

CMOS ASIC lifetime and Physics-of-Faliure (PoF) modeling can be performed at mulitple levels including: System-on-Chip (SoC), Block, Circuit, Device as well as at the atomistic materials level. More computationally efficient methods at the SoC level, well as new compact PoF models at lower device levels, are needed within the device hierarchy that capture relavant reliaiblity degradation mechanisms and processes.

Electronic circuit reliability modeling

Microelectronics Reliability, 2006

The intrinsic failure mechanisms and reliability models of state-of-the-art MOSFETs are reviewed. The simulation tools and failure equivalent circuits are described. The review includes historical background as well as a new approach for accurately predicting circuit reliability and failure rate from the system point of view.

Accurate Quantitative Physics-of-Failure Approach to Integrated Circuit Reliability

Modern electronics typically consist of microprocessors and other complex integrated circuits (ICs) such as FPGAs, ADCs, and memory. They are susceptible to electrical, mechanical and thermal modes of failure like other components on a printed circuit board, but due to their materials, complexity and roles within a circuit, accurately predicting a failure rate has become difficult, if not impossible. Development of these critical components has conformed to Moore's Law, where the number of transistors on a die doubles approximately every two years. This trend has been successfully followed over the last four decades through reduction in transistor sizes creating faster, smaller ICs with greatly reduced power dissipation. Although this is great news for developers and users of high performance equipment, including consumer products and analytical instrumentation, a crucial, yet underlying reliability risk has emerged. Semiconductor failure mechanisms, which are far worse at these minute feature sizes (tens of nanometers), result in higher failure rates, shorter device lifetimes and unanticipated early device wearout. This is of special concern to users whose requirements include long service lifetimes and rugged environmental conditions, such as aerospace, defense, and other high performance (ADHP) industries. To that end, the Aerospace Vehicle Systems Institute (AVSI) has conducted research in this area, and DfR Solutions has performed much of the work as a contractor to AVSI.

Introductory Invited Paper Electronic circuit reliability modeling

The intrinsic failure mechanisms and reliability models of state-of-the-art MOSFETs are reviewed. The simulation tools and failure equivalent circuits are described. The review includes historical background as well as a new approach for accurately predicting circuit reliability and failure rate from the system point of view.

A unified approach for the reliability modeling of MOSFETs

2008 International Conference on Simulation of Semiconductor Processes and Devices, 2008

Modeling capabilities and considerations to achieve a unified reliability model (URM) are addressed. The causes of the trap generation and their effects on the device characteristics serve the unified reliability model. A strategy taken in the SNU group based on the CLESICO system is introduced, where the hydrogen transport and trapping in the gate dielectric to form active carrier trapping sites and their effects on the device characteristics such as the current degradation are treated in a systematic and statistical manner. The treatment of the discrete nature of the trapped charges to model the RTS and 1/f noises are also introduced.

An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology

2007

The de facto modeling method to analyze channel-hot-carrier (CHC) is based on substrate current (Isub), which becomes increasingly problematic with technology scaling as various leakage components dominate Isub. In this work, we present a unified approach that directly predicts the change of key transistor parameters under various process and design conditions, for both negative-bias-temperature-instability (NBTI) and CHC degradation. Using the general reaction-diffusion model and the concept of surface potential, the proposed method continuously captures the performance degradation across subthreshold and strong inversion regions. Models are comprehensively verified with an industrial 65 nm technology. We benchmark the prediction of circuit performance degradation with measured ring oscillator data and simulations of an amplifier.

Towards optimal CMOS lifetime via unified reliability modeling and multi-objective optimization

2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2011

Reliability of CMOS devices emerges as a vital design constraint, evidenced by several CMOS failure mechanisms. Such mechanisms have traditionally been modeled independently, using statistical approximation techniques to estimate Mean-Time-to-Failure (MTTF) rates. This paper proposes a unified framework that integrates the existing failure models into a multi-objective optimization engine, in an attempt to provide a pareto-optimal solution indicating the suggested operating conditions of a system for a given technology and size (in transistors), in an effort to maximize its lifetime reliability. In addition to the existing failure mechanisms, the framework also considers a proposed system-level leakage power estimation model, as leakage is interdependent on temperature, and as such impacts system reliability. The framework can be used in several design scenarios, such as thermal-aware task scheduling.

From defects creation to circuit reliability – A bottom-up approach (invited)

Microelectronic Engineering, 2011

This paper presents a theoretical framework about interface states creation rate from Si-H bonds at the Si/SiO 2 interface. It includes three mains ways of bond breaking. In the first case, the bond can be broken thanks to the bond ground state rising with an electrical field. In the two others cases, incident carriers will play the main role either if there are very energetic or very numerous but less energetic. This concept allows us physically modeling the reliability of MOSFET transistors, and particularly NBTI permanent part, and Channel Hot Carrier (CHC) to Cold Carrier (CCC) damage. Finally, the translation of these physical models into reliability spice models is discussed. These models pave the way to Design-in Reliability (DiR) approach which seeks to provide a quantitative assessment of reliability-CMOS device reliability in this case-at design stage thereby enabling judicious margins to be taken beforehand.

CMOS device design-in reliability approach in advanced nodes

2009 IEEE International Reliability Physics Symposium, 2009

a general framework is proposed to characterize digital library gates for NBTI and HCI ageing effects. Required parameters extraction is demonstrated for practical cases using accurate, state-of-the-art reliability simulation flow. Both NBTI recovery and HCI models are required to accurately assess digital product degradation