Physical Design at the Transistor Level Beyond Standard-Cell Methodology (original) (raw)

This talk offers a review of possibilities to explore on VLSI layout beyond traditional standard cell methodology. Existing Physical Design tools strictly avoid any modification to the contents of Standard Cells. Here, a post-processing step based on SAT solvers is proposed to obtain optimal solutions for local transistor level layout synthesis problems. This procedure can be constrained by metrics that ensure that quality is not degraded, and an acceptable and better-quality timing model can be rebuilt for the block. These problems and techniques are open research opportunities in Physical Design as they are not sufficiently explored in the literature and can bring significant improvements to the quality of a VLSI circuit.