Circuit level, 32nm, 1-bit MOSSI-ULP adder: power, PDP and area efficient base cell for unsigned multiplier (original) (raw)

Low power n-bit adders and multiplier using lowest-number-of-transistor 1-bit adders

Canadian Conference on Electrical and Computer Engineering, 2005., 2005

Select Adders (CSA), and a 4×4 Braun Multiplier, based on lowestnumber-of-Transistor full adders, were designed and simulated. The designed full adders consist of 10 Transistors and were used for n-bit adders with output voltage levels having a maximum of one threshold voltage (V T ) degradation. The 10 Transistors adder achieved a 43.68% reduction in the power dissipation compared to the standard CMOS-28T Adder. Power consumption can be further reduced by using an extra stack transistor. A 12-Transistor Adder was also designed for low area Array Multipliers.

Design of Area Optimized , Low Power , High Speed Multiplier Using Optimized PDP Full Adder

2013

Fast multipliers are essential parts of digital signal processing systems. The speed of multiply operation is of great importance in digital signal processing as well as in the general purpose processors. Now a days, there are an increasing number of portable applications requiring small-area, low power and high throughput circuitry. The circuits with low power consumption become the major issues for the design of microprocessor and system components. The adders and multipliers are the basic elements to construct the ASIC applications. One fast approach to reduce the power dissipation of multiplier is Binary Tree Based Architecture. In BT architecture is based on the generation of all partial products of the multiplication can be done in parallel and then summing these partial products using binary tree network. This method has minimum power consumption with increasing speed of operation. The adders used in the multiplier are designed with multiplexer and four transistor based XOR a...

Comparative Analysis of a Low Power and High Speed Hybrid 1-Bit Full Adder for ULSI Circuits

2016

Full adder circuit is a basic building block for designing any arithmetic circuits. Due to high demands and need for low and high speed digital circuits with small silicon area scaling trends have increased tremendously. In this paper a new high speed full adder circuit is proposed with very less static and dynamic power dissipation which occupies less silicon area when compared with existing techniques. For 1.8-V supply at 180μm technology the average power consumption (0.306mw) was found to be extremely low with a delay of 728.54ps. Correspondingly values of the same are found to be 0.034mw and 44.235ps with 1.2V supply at 130nm technology. The design was further extended for implementing 32-bit full adder and is found to be efficiently working with only 23.3088ns(1.41552ns) delay and 9.792mw(1.088mw) power at 180μm (130nm) technology for 1.8V(1.2V) supply voltage. In comparison with the existing full adder designs the proposed circuit offers significant improvement in terms of ar...

DESIGN OF LOW-POWER FULL ADDER IN 0.18 µm CMOS TECHNOLOGY

With the increase in device integration level and the growth in complexity of Integrated circuits, small delay and low power dissipation become important parameters as these increases performance and portability. Battery storage is limited, to extend battery life; low power operation is the primary requirement in integrated circuits. Furthermore, high speed and multiple parallel applications need high computing power, placing greater demands on energy storage elements within the system. Large power dissipation in high performance digital systems requires large size heat sinks. These off chip component makes chip bulky and require large space. Secondly, extra heat in integrated circuit degrades the system performance. The full adder (FA) is a very important and basic building block in Arithmetic and Logic unit (ALU) of digital processor. The most widely accepted metrics to measure the quality of a digital circuit or to compare various circuit styles is power delay product. Further, Portability imposes a strict limitation on power dissipation while needs more computational speeds. The reduced power consumption and the improved speed require optimizations at all levels of the design procedure.

A DESIGN OF LOW POWER AND LOW AREA MULTIPLIER USING SHIFT AND ADD ARCHITECTURE

In this research work, low power and low area based multiplier architecture is proposed for high speed applications. There are a few enhancement made to the conventional shift and add multiplier architecture, the normal adder for addition has been replaced by the Error Tolerant[ET] concept for designing the adder and activating the adder cells by current multiplication bit of the multiplier constant. In the normal design, carry propagation dissipates the significant amount of dynamic power consumption. In contrast to the existing architectures, in this proposed architecture the multiplexer is removed and when the multiplicand has a zero as a bit the adder is bypassed. Shifting the partial products and multiplier bits is done by using the down counter. The proposed ET shift and add multiplier is synthesized in the XILINX software and simulated in ModelSim. The result for 8x8 multiplier shows the proposed design reduces the power consumption and delay by 55mw and 49ns respectively compared to the existing one. The area, power, and delay optimization is achieved by using the error tolerant shift and add multiplier. Hence making it suitable for image processing application because minimum amount error is tolerable.

Comparative Analysis of 4-bit Multipliers Using Low Power Adder Cells

ijera.com

Multiplier is the most commonly used circuit in the digital devices. Multiplication is one of the basic functions used in digital signal processing. Most high performance DSP systems rely on hardware multiplication to achieve high data throughput. There are various types of multipliers available depending upon the application in which they are used. Full Adder is the main block of power dissipation in multiplier. So reducing the power dissipation of full adder ultimately reduces the power dissipation of multiplier. In this paper 4-bit multipliers based on Gate Diffusion Input (GDI) adder cells are compared using EDA Tanner (Evaluation version), simulations are based on 180nm CMOS technology.

Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL

VLSI Design, 2013

Asynchronous adiabatic logic (AAL) is a novel lowpower design technique which combines the energy saving benefits of asynchronous systems with adiabatic benefits. In this paper, energy efficient full adder using double pass transistor with asynchronous adiabatic logic (DPTAAL) is used to design a low power multiplier. Asynchronous adiabatic circuits are very low power circuits to preserve energy for reuse, which reduces the amount of energy drawn directly from the power supply. In this work, an 8×8 multiplier using DPTAAL is designed and simulated, which exhibits low power and reliable logical operations. To improve the circuit performance at reduced voltage level, double pass transistor logic (DPL) is introduced. The power results of the proposed multiplier design are compared with the conventional CMOS implementation. Simulation results show significant improvement in power for clock rates ranging from 100 MHz to 300 MHz.

[2008] Low power multipliers based on new hybrid full adders

Five hybrid full adder designs are proposed for low power parallel multipliers. The new adders allow NAND gates to generate most of the multiplier partial product bits instead of AND gates, thereby lowering the power consumption and the total number of needed transistors. For an 8 Â 8 implementation, the ALL-NAND array multiplier achieves 15.7% and 7.8% reduction in power consumption and transistor count at the cost of a 6.9% increase in time delay compared to standard array multiplier. The ALL-NAND tree multiplier exhibits lower power consumption and transistor count by 12.5% and 7.3%, respectively, with a 4.4% longer time delay, compared to conventional tree multiplier.

BZ-FAD: A Low-Power Low-Area Multiplier based on Shift-and-Add Architecture

In this paper, a low-power structure called BZ-FAD (Bypass Zero, Feed A Directly) for shift-and-add multipliers is proposed. The architecture considerably lowers the switching activity of conventional multipliers. The modifications to the multiplier which multiplies A by B include the removal of the shifting the B register, direct feeding of A to the adder, bypassing the adder whenever possible, using a ring counter instead of a binary counter and removal of the partial product shift. The architecture makes use of a low-power ring counter proposed in this work. Simulation results for 32-bit radix-2 multipliers show that the BZ-FAD architecture lowers the total switching activity up to 76% and power consumption up to 30% when compared to the conventional architecture. The proposed multiplier can be used for low-power applications where the speed is not a primary design parameter.

An Improved Low Power, High Speed CMOS Adder Design for Multiplier

An improved CMOS full adder circuit for high speed and low power applications is proposed in this paper at 90 nm technology node with supply voltage 1.2 V. The proposed designs contain implementation of sum and carry circuit separately. The adder circuit contains carry circuit with transmission gate logic, which is the power reduction logic in any digital circuitry. Transmission logic decrease transistor count of our proposed carry circuitry. The proposed design gives 53% reduction in power, 63 % reduction in delay, respectively. A 2-bit multiplier is made using the proposed adder circuit which results in very less power consuming and very fast in operation in compared to the other multiplier circuits.