A monolithic buck DC–DC converter with on-chip PWM circuit (original) (raw)
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Monolithic buck converter for CMOS process technologies
2008 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
Monolithic switching buck (step-down) converter is designed on standard 0.35-µm CMOS process. Different control techniques such as Pulse-Width Modulations (PWM) and Pulse-Frequency Modulations (PFM) are investigated. The received results show that PFM control indicates higher efficiency at light-loads compare to standard constant frequency PWM control. Efficiency of about 76 % is achieved for the PWM control at switching frequency of 150 MHz for voltage conversion from 3.6 down to 1.2V. I.
A Monolithic Current-Mode Buck Converter With Advanced Control and Protection Circuits
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A monolithic current-mode pulse width modulation (PWM) step-down dc-dc converter with 96.7% peak efficiency and advanced control and protection circuits is presented in this paper. The high efficiency is achieved by "dynamic partial shutdown strategy" which enhances circuit speed with less power consumption. Automatic PWM and "pulse frequency modulation" switching boosts conversion efficiency during light load operation. The modified current sensing circuit and slope compensation circuit simplify the current-mode control circuit and enhance the response speed. A simple high-speed over-current protection circuit is proposed with the modified current sensing circuit. The new on-chip soft-start circuit prevents the power on inrush current without additional off-chip components. The dc-dc converter has been fabricated with a 0.6 m CMOS process and measured 1.35 mm 2 with the controller measured 0.27 mm 2. Experimental results show that the novel on-chip soft-start circuit with longer than 1.5 ms soft-start time suppresses the power-on inrush current. This converter can operate at 1.1 MHz with supply voltage from 2.2 to 6.0 V. Measured power efficiency is 88.5-96.7% for 0.9 to 800 mA output current and over 85.5% for 1000 mA output current.
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An analysis of an on-chip buck converter is presented in this paper. A high switching frequency is the key design parameter that simultaneously permits monolithic integration and high efficiency. A model of the parasitic impedances of a buck converter is developed. With this model, a design space is determined that allows integration of active and passive devices on the same die for a target technology. An efficiency of 88.4% at a switching frequency of 477 MHz is demonstrated for a voltage conversion from 1.2-0.9 volts while supplying 9.5 A average current. The area occupied by the buck converter is 12.6 mm assuming an 80-nm CMOS technology. An estimate of the efficiency is shown to be within 2.4% of simulation at the target design point. Full integration of a high-efficiency buck converter on the same die with a dual-microprocessor is demonstrated to be feasible.
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This paper includes investigations of power losses in monolithic buck dc-dc converter designed with Cadence on CMOS 0.35 μm process. Input voltage of the designed circuit is equal to 3.6 V and output voltage is regulated to 1.2 V. Evaluated and estimated are power dissipations in the MOS transistor, filter inductor and filter capacitor of the buck converter. Investigated and compared are losses in the offchip filter inductors of the company Murata and on-chip filter inductors. For the extraction of the model’s parameters of integrated inductors CMOS 0.35 μm process is used “Virtuoso Passive Component Designer”.
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Fourth International Symposium on Quality Electronic Design, 2003. Proceedings., 2003
The design of an efficient monolithic buck converter is presented in this paper. A low swing MOSFET gate drive technique is proposed that improves the efficiency characteristics of a DC-DC converter. A model of the parasitic impedances of a buck converter is developed. With this model, a design space is described which characterizes the integration of both active and passive devices of a buck converter onto the same die based on a 0.18 µm CMOS technology. The optimum gate voltage swing of a power MOSFET that maximizes efficiency is shown to be lower than a standard full voltage swing. An efficiency of 88% at a switching frequency of 102 MHz is achieved for a voltage conversion from 1.8 volts to 0.9 volts with a low swing DC-DC converter. The power dissipation of a low swing DC-DC converter is reduced by 24.5%, improving the efficiency by 3.9% as compared to a full swing DC-DC converter.
A Monolithic Current-Mode CMOS DC–DC Converter With On-Chip Current-Sensing Technique
A monolithic current-mode CMOS DC-DC converter with integrated power switches and a novel on-chip current sensor for feedback control is presented in this paper. With the proposed accurate on-chip current sensor, the sensed inductor current, combined with the internal ramp signal, can be used for current-mode DC-DC converter feedback control. In addition, no external components and no extra I/O pins are needed for the current-mode controller. The DC-DC converter has been fabricated with a standard 0.6-m CMOS process. The measured absolute error between the sensed signal and the inductor current is less than 4%. Experimental results show that this converter with on-chip current sensor can operate from 300 kHz to 1 MHz with supply voltage from 3 to 5.2 V, which is suitable for single-cell lithium-ion battery supply applications. The output ripple voltage is about 20 mV with a 10-F off-chip capacitor and 4.7-H off-chip inductor. The power efficiency is over 80% for load current from 50 to 450 mA.
A compact CMOS DC‐DC buck converter based on a novel complement value leaping PWM technique
International Journal of Circuit Theory and Applications, 2019
A very compact ultra-low power DC-DC buck converter is presented. The proposed buck converter employs a novel complement value leaping pulsewidth modulation (PWM) technique to realize the desired DC mean-value for various loads. Incorporating just two counters with a simple digital controller to load the repeatedly complemented value of the 4bit up/down counter as the initial value of the least significant bits of the 5bit up counter, a PWM pulse is created to manage the charge/recharge period. The realized PWM signal maintains the same desired output voltage mean value for any load resistance between 80 and 140 Ω. The switching frequency is 160 kHz, and the overall power consumption is 26.9 nW, while the efficiency is 93.4% for current range of 1.7 to 3 mA. The performance of the proposed converter is validated by Cadence post-layout simulations utilizing TSMC180nm CMOS technology for 1-V supply voltage providing the output voltage mean value of 0.24 V.
IEEE Journal of Solid-State Circuits, 2004
An integrated adaptive-output switching converter is presented. This converter adopts one-cycle control for fast line response and dual error correction loops for tight load regulation. A dc level shifting technique is proposed to eliminate the use of negative supply and reference voltages in the controller and make the design compatible with standard digital CMOS process. The design accommodates both continuous and discontinuous conduction operations. To further enhance the efficiency, dynamic loss control on the power transistors is proposed to minimize the sum of switching and conduction losses. The design can be extended to other dc-dc and ac-dc conversions. The prototype of the buck converter was fabricated with a standard 0.5m digital CMOS process. Experimental results show that the converter is well regulated over an output range of 0.9-2.5 V, with a supply voltage of 3.3 V. The tracking speeds are 12.25 s V for a 1.6-V step-up output change and 13.75 s V for a 1.6-V step-down output change, respectively, which are much faster than existing counterparts. Maximum efficiency of 93.7% is achieved and high efficiency above 75% is retained over an output power ranging from 10 to 450 mW.
2002
An analysis of the power characteristics of a buck converter is presented in this paper. A high switching frequency is the key design parameter that simultaneously permits monolithic integration and high efficiency. A parasitic model of the buck converter is developed. With this model, a design space is determined that allows integration of active and passive devices on the same die for a target technology. An efficiency of 88.4% at a switching frequency of 477 MHz is demonstrated for a voltage conversion from 1.2 volts to 0.9 volts while supplying 9.5 amperes average current assuming an 80 nm CMOS technology. The area occupied by the buck converter is 12.6 mm 2 . An analytic estimate of the efficiency is shown to be within 2.4% of simulation at the target design point. Full integration of a high efficiency buck converter on the same die with a dual-V DD microprocessor is shown to be feasible.