Architecture and Physical Implementation of a Third Generation 65 nm, 16 Core, 32 Thread Chip-Multithreading SPARC Processor (original) (raw)

Architecture and Physical Implementation of a Third Generation 65 nm, 16 Core, 32 Thread Chip-Multithreading SPARC Processor

IEEE Journal of Solid-State Circuits, 2009

Abstract

Abstract This third-generation Chip-Multithreading (CMT) SPARC processor consists of 16 cores with shared memory architecture and supports a total of 32 main threads plus 32 scout threads. It is targeted for high-performance servers, and is optimized for both single-and ...

mamun rashid hasn't uploaded this paper.

Let mamun know you want this paper to be uploaded.

Ask for this paper to be uploaded.