Μηχανισμοί αδιαμεσολάβητης επικοινωνίας και συγχρονισμού για πολυεπεξεργαστές ψηφίδας (original) (raw)

Μηχανισμοί αδιαμεσολάβητης επικοινωνίας και συγχρονισμού για πολυεπεξεργαστές ψηφίδας

2010

Abstract

The physical constraints of transistor integration have made chip multiprocessors (CMPs) a necessity, and increasing the number of cores (CPUs) the best approach, yet, for the exploitation of more transistors. Already, the feasible number of cores per chip increases beyond our ability to utilize them for general purposes. Although many important application domains can easily benefit from the use of more cores, scaling, in general, single-application performance with multiprocessing presents a tough milestone for computer science. The use of per core on-chip memories, managed in software with RDMA, adopted in the IBM Cell processor, has challenged the mainstream approach of using coherent caches for the on-chip memory hierarchy of CMPs. The two architectures have largely different implications for software and disunite researchers for the most suitable approach to multicore exploitation. We demonstrate the combination of the two approaches, with cache-integration of a network interf...

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