CMOS Technology Dedicated to Low Power Consumption Wireless Applications (original) (raw)
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A 65-NM CMOS RF Mixer for Different Applications
2015
A down conversion RF mixer is designed with 65nm CMOS technology for a different low power consumption applications. Mixer structure comprises a double-balanced Gilbert-Cell with improving linearity method in the RF stage of circuit; all is at a supply voltage of 1.8V and a power of 2.17 mW. The circuit is simulated for different spectrum applications as: 200 MHz mobile users, 1.9 GHz wireless applications, and 20 to 60 GHz commercial satellite and pointtopoint communications. The reported design achieves good values in terms of a radio frequency mixer evaluating parameters such as: Consumed Power, Conversion Gain, Noise Figure and Linearity.
Microelectronics, Electromagnetics and Telecommunications, Volume 372, Lecture Notes in Electrical Engineering, pp 485-495, 2015
This paper discusses the design of a 2.4 GHz operated, ultra-low power CMOS down-converting active mixer based on double balanced Gilbert-cell resistor-loaded topology fabricated in standard 180 nm RF CMOS low-power technology. All the MOS transistors of the mixer core have ideally been biased to sub-threshold region. Consuming only 500 μW of DC power using 1.0 V supply and minimal LO power of −16 dBm, this mixer demonstrates a simulated power conversion gain of 17.2 dB with Double Side Band (DSB) noise figure of 13.3 dB. With the same DC power dissipation and LO power, −11.7 dBm IIP3 and −20.1 dBm 1-dB point have been obtained as discussed in the paper. Pre-layout and post layout simulation results match very well. The ultra-low power consumption of the proposed mixer due to subthreshold region of operation and lower local oscillator power are the advantages of this subthreshold mixer.
mm-wave CMOS mixer design in 65 nm technology for 60 GHz wireless communications
2009
This paper describes the design of a double balanced mixer known as a Gilbert cell mixer. The proposed design, which operates at a radiofrequency (RF) of 1.9 GHz, is implemented in 0.18 μm CMOS technology at a supply voltage of 1.8 V. The components values and the size of CMOS transistors used to achieve a better linearity while keeping a good conversion gain are calculated. The obtained results show a third order input intercept point (IIP3) and an 1-dB compression point in the order of 10.5 dBm and -2 dBm, respectively when the conversion gain roughly equal to 9.12 dB. These performances justify the good linearity of the mixer compared to those using an inductive degeneration or active loads like P-channel MOS. Key words: Mixer, Gilbert cell, degeneration resistor, conversion gain, linearity.