A Survey Analysis on CMOS Integrated Circuits with Clock-Gated Logic Structure (original) (raw)

Noise Tolerant Circuits for Modified Feedthrough Logic

2013

In this paper a circuit design technique to improve noise tolerant of a new CMOS domino logic family called feedthrough logic is presented. The feedthrough logic improves the performance of arithmetic circuit as compared to static CMOS and domino logic but its noise tolerant is very less. A 2-input NAND gate is designed by the proposed technique. The ANTE (average noise threshold energy) metric is used for the comparison of noise tolerance of proposed circuit with the feedthrough logic. Simulation results for a 2- input NAND gate at 0.18-µm, 1.8 V CMOS process technology show that the proposed noise tolerant circuit achieves 1.79X ANTE improvement along with the reduction leakage power.

High-performance noise-tolerant circuit techniques for CMOS dynamic logic

IET Circuits, Devices & Systems, 2008

Dynamic CMOS gates are widely exploited in high-performance designs because of their speed. However, they suffer from high noise sensitivity. The main reason for this is the sub-threshold leakage current flowing through the evaluation network. This problem becomes more and more severe with continuous scaling of the technology. A new circuit technique for increasing the noise tolerance of dynamic CMOS gates is studied. A comparison with previously reported schemes is presented. Simulations proved that, when 90 nm CMOS technology is used to realise wide fan-in gates, the proposed design technique can achieve the highest level of noise robustness. A 16 bits OR gate designed as proposed here shows a maximum unity noise gain of 675 mV, a computational delay of 115 ps and an energy dissipation of 33 fJ. Moreover, at the parity of energy-delay product (EDP), the novel approach achieves a noise robustness 10% higher than the most efficient technique existing in the literature, whereas, at the parity of noise robustness, it exhibits an EDP 33% lower. Recently, several techniques have been proposed to reduce the leakage noise sensitivity of high fan-in footless domino gates [4-13]. All the existing techniques improve the noise

On circuit techniques to improve noise immunity of CMOS dynamic logic

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000

Dynamic CMOS logic circuits are widely employed in high-performance VLSI chips in pursuing very high system performance. However, dynamic CMOS gates are inherently less resistant to noises than static CMOS gates. With the increasing stringent noise requirement due to aggressive technology scaling, the noise tolerance of dynamic circuits has to be first improved for the overall reliable operation of VLSI chips designed using deep submicron process technology. In the literature, a number of design techniques have been proposed to enhance the noise tolerance of dynamic logic gates. An overview and classification of these techniques are first presented in this paper. Then, we introduce a novel noise-tolerant design technique using circuitry exhibiting a negative differential resistance effect. We have demonstrated through analysis and simulation that using the proposed method the noise tolerance of dynamic logic gates can be improved beyond the level of static CMOS logic gates while the performance advantage of dynamic circuits are still retained. Simulation results on large fan-in dynamic CMOS logic gates have shown that, at a supply voltage of 1.6 V, the input noise immunity level can be increased to 0.8 V for about 10% delay overhead and to 1.0 V for only about 20% delay overhead.

An Improved Noise-Tolerant Domino Logic Circuit for High Fan-in Gates

2005

Dynamic logic circuits are used for high performance circuits. Wide OR gates are employed for high speed processors, DRAM, SRAM and high speed logic circuits. Dynamic logic circuits are used for their high performance, but their high noise and extensive leakage has caused some problems for these circuits. However, dynamic CMOS circuits are inherently less resistant to noise than static CMOS gates. So, for dynamic CMOS, the first improvement has to be noise tolerance for the overall reliable operation of VLSI chips designed using deep submicron process technology. In this paper, we propose a new domino logic circuit scheme to reduce subthreshold leakage current in standby mode and to improve noise immunity for wide OR gates. The conditions for our simulations are: Berkeley CMOS 70nm predictive technology for simulated results [1], 0.9V power supply and bottleneck operating temperature of 110°C. Simulation results on 8, 16, 32 and 64 inputs OR gates showed improvements from 2.116X to 15.83X compared with other conventional techniques. Furthermore, while there is an area overhead of 13% compared with 8-input FLSDL, we have achieved a decreased area of 5%, 23% and 33% compared with 16, 32, and 64-input footless standard domino logic (FLSDL) respectively.

Noise Immunity Investigation of Low Power Design Schemes(Electronic Circuits)

Ieice Transactions on Electronics, 2006

In modern CMOS digital design, the noise immunity has come to have an almost equal importance to the power consumption. In the last decade, many low power design schemes have been presented. However, no one can simply judge which one is the best from the noise immunity point of view. In this paper, we investigate the noise immunity of the static CMOS low power design schemes in terms of logic and delay errors caused by different kinds of noise existing in the static CMOS digital circuits. To fulfill the aims of the paper, first a model representing the different sources of noise in deep submicron design is presented. Then the model is applied to the most famous low power design schemes to find out the most robust one with regard to noise. Our results show the advantages of the dual threshold voltage scheme over other schemes from the noise immunity point of view. Moreover, it indicates that noise should be carefully taken into account when designing low power circuits; otherwise circuit performance would be unexpected. The study is carried out on three circuits; each is designed in five different schemes. The analysis is done using HSPICE, assuming 0.18 µm CMOS technology.

Evaluation of power supply noise in CMOS and low noise logic cells

2008 Asia-Pacific Symposium on Electromagnetic Compatibility and 19th International Zurich Symposium on Electromagnetic Compatibility, 2008

In digital designs, it becomes more and more important to reduce the supply current variations (di/dt noise) they induce in the supply lines. This is due to the fact that steep variations in supply current give rise to EM (Electro-Magnetic) radiation. In this paper, two new modified low-noise logic styles-Complementary-CBL (C-CBL) and Enhanced-CSL (E-CSL) are presented in which the di/dt noise due to the switching is reduced greatly with respect to standard CMOS (SCMOS) circuits. Furthermore, a comparison with existing alternative low noise techniques shows that, for the same supply voltage and the same power consumption, the Enhanced-CSL circuits have smaller area, higher noise margins and smaller propagation delay.

A Review of Noise Susceptible Transistor in Dynamic Logic Circuits

International Journal of Computer Applications, 2014

Noise is becoming a major concern in digital systems due to the insistent scaling development in devices and interconnections. In this paper disputes related to process variations, timing, noise suppression, and power are investigated here for performance optimization. A weak PMOS keeper logic is used to improve the scaling of dynamic gates. The keeper has an overhead of one field-effect transistor per gate plus a portion of a shared current mirror. This keeper circuit technique is proposed in this paper for simultaneous power reduction and speed enhancement of domino integrated circuits. The threshold voltage of the keeper logic is modified during circuit operation to decrease the contention current without giving up noise immunity. The charge sharing can also be eliminated by pre-charging internal node.

IJERT-CS-CMOS: A Low Noise Logic Family for Mixed Signal Integrated Circuits

International Journal of Engineering Research and Technology (IJERT), 2016

https://www.ijert.org/cs-cmos-a-low-noise-logic-family-for-mixed-signal-integrated-circuits https://www.ijert.org/research/cs-cmos-a-low-noise-logic-family-for-mixed-signal-integrated-circuits-IJERTV5IS010510.pdf In low-power CMOS logic circuits operated from a fixed supply voltage can result in uncontrolled conduction over process and temperature variation. The large current-pulses flowing during the logic transitions also cause power-supply noise. Managing the switching-noise in mixed-signal systems fabricated on a single chip is becoming increasingly challenging. Here we introduce a new logic family called CS-CMOS (Current Steering-CMOS) which is obtained by a simple current steering modification to the core CMOS structure. This is a low-noise logic family, so its main application is in the field of mixed signal system-on-chips (SoCs). Existing logic families that minimize the switching-noise generation such as current-steering logic (CSL), current-balanced logic (CBL) etc. require considerably more power than traditional CMOS implementations. But all of these logics reduces switching noise and also improves the switching speed compared to conventional CMOS logic. The current steered CMOS gates (CSCMOS) are specially targeted for use in low-power, wide dynamic range mixed-signal applications where supply noise must be minimized. Analysis for different parameters like power consumption, delay and noise generated are done in cadence using different technologies and compared its performance. Circuit operation and simulation results are presented. Keywords-Current-balanced logic (CBL), current steering logic (CSL),current-steering CMOS (CS-CMOS), mixed signal system-on-chip (SoC), power supply noise.

Improved Power Gating Techniques for Reduction of Noise and Leakage Power in VLSI Circuits

Design of complex arithmetic logic circuits considering ground noise, leakage current, active power and area is a challenging task in VLSI circuits. In this paper, a comparative analysis of high performance power gating schemes is done which minimizes the leakage power and provides a way to control the ground noise. The innovative power gating schemes such as stacking power gating , diode based stacking power gating are analyzed which minimizes the peak of ground noise in transition mode for deep submicron circuits. Further to evaluate the efficiency, the simulation has been done using such high performance power gating schemes. Leakage current comparison of NAND gate without power gating and with power gating scheme is done. Finally it is observed that the leakage current in standby mode is reduced by 80% over the conventional power gating. It is also found that in stacking power gating, the ground noise has been reduced by a small extent over the conventional power gating scheme. We have performed simulations using Tanner in a 180nm standard CMOS technology at room temperature with supply voltage of 2.5 V. Finally, a detailed comparative analysis has been carried out to measure the design efficiency of high performance power gating schemes. This analysis provides an effective road map for high performance digital circuit designers who are interested to work with low power application in deep submicron circuits.