Design and Analysis of Low-Power 11- Transistor Full Adder (original) (raw)

DESIGN OF LOW-POWER FULL ADDER IN 0.18 µm CMOS TECHNOLOGY

With the increase in device integration level and the growth in complexity of Integrated circuits, small delay and low power dissipation become important parameters as these increases performance and portability. Battery storage is limited, to extend battery life; low power operation is the primary requirement in integrated circuits. Furthermore, high speed and multiple parallel applications need high computing power, placing greater demands on energy storage elements within the system. Large power dissipation in high performance digital systems requires large size heat sinks. These off chip component makes chip bulky and require large space. Secondly, extra heat in integrated circuit degrades the system performance. The full adder (FA) is a very important and basic building block in Arithmetic and Logic unit (ALU) of digital processor. The most widely accepted metrics to measure the quality of a digital circuit or to compare various circuit styles is power delay product. Further, Portability imposes a strict limitation on power dissipation while needs more computational speeds. The reduced power consumption and the improved speed require optimizations at all levels of the design procedure.

IJERT-Power Efficient CMOS Full Adders with Reduced Transistor Count

International Journal of Engineering Research and Technology (IJERT), 2014

https://www.ijert.org/power-efficient-cmos-full-adders-with-reduced-transistor-count https://www.ijert.org/research/power-efficient-cmos-full-adders-with-reduced-transistor-count-IJERTV3IS031276.pdf In this Paper, a CMOS Full Adder is designed using Tanner EDA Tool based on 0.25μm CMOS Technology. Using Tanner software tools, schematic and simulations of CMOS full adder are designed and presented, which helps to obtain design constraints. As part of this we have performed the simulation of CMOS full adder using T-SPICE of Tanner EDA. This paper also proposes a new 3T-XOR gate with significant area and power savings. A new eight transistors one bit full adder based on 3T-XOR gate is presented. Simulations results utilizing standard 0.25μm CMOS technology illustrate a significant improvement in terms of number of transistors, chip area and propagation delay.

Modified Low-Power Hybrid 1-Bit Full Adder

2018

The usage of digital devices is increasing rapidly and they became essential part of everyone’s life. Digital devices can be designed according to their application and most of them are realized using arithmetic processor which consists of several operations like addition, subtraction, multiplication, etc., all of them can be implemented using full adder as the basic building block. As full adder plays a major role in digital devices we need to design a low-power full adder such that the devices can operate at lower power consumption and has longer battery life. In this research work, a hybrid low-power 1-bit full adder was designed using CMOS logic, pass transistor, and transmission gate logic with 14 transistor. The design was simulated using HSPICE tools in 90 nm technology with supply voltage of 1.2 V. Performance parameters, such as power, delay, and power delay product were compared with the existing designs, such as C-CMOS Full Adder, Mirror adder, hybrid pass-logic with stat...

Design And Analysis Of Low Power High Performance Single Bit Full Adder

Adder is the significant circuit in arithmetic operations. Adder cells are designed for power and delay reduction. Now ground bounce noise is also necessary for good performance. In this paper the full adder is designed using only 8 Transistors using Pass Transistor Logic (PTL). The power gating technique is one such a best technique which reduces leakage power through the ground. This technique is implemented using sleep transistor added between ground rail and actual ground. Here a single bit 8 Transistor full adder is proposed. We will perform analysis and simulation of various parameters like power, delay and ground bounce noise using tanner EDA tool 180nm CMOS Technology.

Implementation of Low Power CMOS Full Adders Using Pass Transistor Logic

The efficiency of a system mainly depends on the performance of internal components present in the system. The internal components should be designed in such a way that they consume low power with high speed. Lot of components is in circuits including full-adder. This is mainly used in processors. A new Pass transistor full adder circuit is implemented in this paper. The main idea is to introduce the design of high performance and based pass transistor full adders which acquires less area and transistor count. The high performance of pass transistor low power full adder circuit is designed and the simulation has been carried out on Tanner EDA Tool. The result shows that the proposed full adder is an efficient full adder cell with least MOS transistor count that reduces the high power consumption and increases the speed. In this paper CMOS full adder circuits are designed to reduce the power and area and to increase the speed of operation in arithmetic application. To operate at ultra-low supply voltage, the pass logic circuit that cogenerates the intermediate XOR and XNOR outputs has been improved to overcome the switching delay problem

LOW-POWER 1-BIT FULL-ADDER CELL USING ENHANCED PASS TRANSISTOR LOGIC AND POWER GATING

Adders have become one of the important components in the digital world, such that there exists no design without it. Adders are not only used for additions, but it is also one of the basic building blocks that have been used for many other functions such as subtractions, multiplications, and divisions etc. In the field of Very Large Scale Integration (VLSI), Adders are used as the basic component from processors to ASICs. Propagation delay, Power and Area are the acceptable Quality metrics of the designed products. Recent days has proved that the use of Complementary Pass Transistor Logic (CPL) and sleep transistor provides a drastic reduction in the power compared to CMOS logic. Power Gating is one such well known technique where a sleep transistor is added between actual ground rail and circuit ground. The device is turned off during sleep mode to cut-off the leakage path. This technique results in a substantial reduction in leakage at a minimal impact on performance. This paper has spread the focus on Low power Adder design based on PTLs, with reduced sub threshold leakage power consumption and ground bounce noise during sleep to active mode transition, thereby achieving 2.5% reduction in power without affecting other quality metrics of the design. The CPL design has been modeled and analyzed using TANNER EDA with TSMC MOSIS 250nm technology. In the present paper we will propose low leakage 1 bit CMOS full adder circuit in 90nm technology with supply voltage of 1V. Keywords: CPL, Power, VLSI, Adder

Design of Energy-Efficient Full Adders Using Hybrid-CMOS Logic Style

IJAET Jan-2012 ISSN, 1963

We present new designs for full adder featuring hybrid-CMOS design style. The quest to achieve a gooddrivability, noise-robustness and low energy operations guided our research to explore hybrid-CMOS style design. Hybrid-CMOS design style utilizes various CMOS logic style circuits to build new full adders with desired performance. We also classify hybrid-CMOS full adders into three broad categories based upon their structure. Using this categorization, many full adder designs can be conceived. The new full adder is based on XOR-XOR Hybrid CMOS model that gives XOR and XOR full swing output simultaneously. This circuit's outperforms its counterparts showing 4%-31% improvement in power dissipation and delay. The output stage also provides good driving capability and no buffer connection is needed between cascaded stages. During our experiments, we found out that many of the previously reported adders suffered from the problems of low swing and high noise when operated at low supply voltages. The proposed full adders are energy efficient and outperform several standard full adders without trading of driving capabilities and reliabilities. The new fulladder circuits successfully operate at low voltages with excellent signal integrity and driving capability. The new adders displayed better performance as compared to the standards full adder. The problem we face during the experiment leads us to different zones where efficient circuit can be developed using this new full adder.

A Review of 1-Bit Full Adder Design Using Different Dynamic CMOS Techniques

2021

The Domino CMOS Logic Circuits are famously utilized in Very Large Scale Integrated (VLSI) structure. To design a VLSI circuit having low power and fast execution or high speed is the most testing task. By and by, one of the main goals is low power VLSI circuits with high speed. Full Adders are mainly used in various circuits which can perform various errands like development, duplication, division etc. In this manner it will diminish the force usage in full adders expects an enormous part of VLSI circuits having low power. In this paper, domino logic is used to manage a stable, particularly improved response for two constraints in full adder circuits i.e. power and delay. We review the Power, Delay and Power Delay Product (PDP) of 22T Domino Full Adder, 27T Domino Full Adder and 28T Static Full Adder. In this we also review these 3 circuit on the basis of different technology nodes or the feature length i.e. 45nm, 90nm and 180nm.

DESIGN OF ENERGY-EFFICIENT FULL ADDER USING HYBRID-CMOS LOGIC STYLE Copyright IJAET

We present new designs for full adder featuring hybrid-CMOS design style. The quest to achieve a good-drivability, noise-robustness and low energy operations guided our research to explore hybrid- CMOS style design. Hybrid-CMOS design style utilizes various CMOS logic style circuits to build new full adders with desired performance. We also classify hybrid-CMOS full adders into three broad categories based upon their structure. Using this categorization, many full adder designs can be conceived. The new full adder is based on XOR-XOR Hybrid CMOS model that gives XOR and XOR full swing output simultaneously. This circuit’s outperforms its counterparts showing 4%-31% improvement in power dissipation and delay. The output stage also provides good driving capability and no buffer connection is needed between cascaded stages. During our experiments, we found out that many of the previously reported adders suffered from the problems of low swing and high noise when operated at low supply voltages. The proposed full adders are energy efficient and outperform several standard full adders without trading of driving capabilities and reliabilities. The new full-adder circuits successfully operate at low voltages with excellent signal integrity and driving capability. The new adders displayed better performance as compared to the standards full adder. The problem we face during the experiment leads us to different zones where efficient circuit can be developed using this new full adder.