A Universal UHF RFID Reader IC in 0.18-µm CMOS Technology (original) (raw)

A Single-Chip UHF RFID Reader in 0.18 muhboxm\mu{\hbox {m}}muhboxm CMOS Process

IEEE Journal of Solid-State Circuits, 2008

A single-chip UHF RFID reader that integrates all building blocks-including an RF transceiver, IQ data converters, and a digital baseband-is implemented in a 0.18 m CMOS process. A high-linearity RX front-end and a low-phase-noise synthesizer are proposed to handle the large self-interferer, which is a key challenge in the reader RX design. Highly reconfigurable mixed-signal baseband architecture for channel-selection filtering is proposed to achieve power optimization for multi-protocol operation with different system dynamic ranges and data rates. The reader dissipates a maximum power of 276.4 mW when transmitting maximum output power of 10.4 dBm and receiving the tag's response of 70 dBm in the presence of 5 dBm self-interferer while occupying 18.3 mm 2 .

System design considerations of universal UHF RFID reader transceiver ICS

Facta universitatis - series: Electronics and Energetics, 2015

This paper describes the architecture, system analysis and implementation of world-wide regulation compliant UHF RFID reader transceiver for ISO 18000-6 multi-class tags in the ISM band 860 MHz-960 MHz. The presented considerations are based on a system analysis providing evaluation of the transceiver?s building blocks parameters in accordance with the required characteristics of a complete RFID reader system, read range, data transmission rate, reading speed and power consumption. The Phase Noise, Noise Figure, Sensitivity, P1dB, Dynamic Range are estimated for the design of a custom ?system-in-package? transceiver, implemented in LTCC-module. Based on the direct-conversion architecture, the reader transceiver integrates RF-blocks, frequency synthesizer, modulation and demodulation functions, low frequency analog baseband. The receiver sensitivity is down to -85 dBm, the transmitter produces output power of +17 dBm.

A Design of a High-Performance Analog Front-End for Passive UHF RFID Tag EPC C1G2

Journal of Communications Software and Systems, 2018

This paper introduces a high-performance analog front end for passive UHF RFID tag compatible with the EPC Class-1 Generation 2 (EPC C1G2) standard protocol. The proposed front end of a passive tag which contains the following modules: a power generation circuit which is composed of a matching circuit and an RF-limiter circuit, an NMOS rectifier, a DC limiter, a voltage regulation, a modulation and ASK demodulation circuit, a power-on-reset circuit, a ring oscillator which generates a clock of 1.28 MHz. The originality of this work is the proposal of a voltage regulation circuit composed of two distinct LDO regulators that share the same reference voltage and are designed to generate a Vdd1 (0.5 V) for the analog supply and Vdd2 (1 V) for digital power supply, under conditions of 50 Ω antenna, 900 MHz, a sensitivity of-24 dBm and a maximum consumption of 1 µW. The operating distance of the RFID is more than 25 meters based on the regulated 4 W effective isotropic radiated power (EIRP). The chip area of the proposed analog front end is only 79 μm × 83 μm. The simulation results in 90 nm CMOS process confirm the performance of the proposed analog front-end. Index Terms-Radio frequency identification (RFID), frontend, ultra-high frequency (UHF), RFID Tag, regulator, clock. I. INTRODUCTION The ultra-high frequency (UHF) passive radio frequency identification (RFID) tags are showing a wide range of prospective applications due to their advantages of low cost, long operating distance, high data rate, and small antenna size [1]. The passive RFID tags working at frequencies between 860 MHz to 960 MHz, and 2.4 GHz are suitable for long distance identification. Long distance identification is important in warehouse monitoring, supply-chain management, logistics, and many other areas [2], [3]. The RFID tags are classified into three types of RFID tags, especially passive [4], [5], semi-passive [6], or active.

A 12 dB 0.7 V W CMOS LNA for 866 MHz UHF RFID Reader

Active and Passive Electronic Components, 2010

The design of a narrow-band cascode CMOS inductive source-degenerated low noise amplifier (LNA) for 866 MHz UHF RFID reader is presented. Compared to other previously reported narrow-band LNA designs, in this paper the finite effect has been considered to improve the nanometric design, achieving simultaneous impedance and minimum noise matching at a very low power drain of 850 from a 0.7 V supply voltage. The LNA was fabricated using the IBM 130 nm CMOS process delivering a forward power gain () of , a reverse isolation () of , an output power reflection ( @866 MHz) of , and an input power reflection ( @866 MHz) of . It had a minimum pass-band of around 2.2 dB and a third-order input referred intercept point (IIP3) of .

A new CMOS radio for low power RFID applications

2010

A novel radio receiver circuit, functioning as a tuned active, detecting antenna, is described. The receiver is suggested to be part of a new radio system with the potential of competing with the range capability of active RFID-tags and, through its low power and long lifetime, with passive RFID-tags. The circuit is outlined and the functionality is verified by simulations and measurements.

ASK compatible CMOS receiver for 13.56 MHz RFID reader

This study concerns about a high frequency companionable receiver architecture for RFID application, which is capable of dealing with most of the previous inadequacies. In this paper, an assessment of different receiver systems is shown and a simulated design of an integrated receiver for 13.56 MHz RFID Reader is proposed for 0.18μm CMOS technology. The design is mainly composed of amplifier, detector and digitizer. The system uses fewer components then that of other CMOS based RFID receivers and consumes a power of 0.325 mWatt at 1V biasing. Synthesized Results show smaller ripple (<0.0002%) than that of existing systems.

CMOS Fully Integrated 2.5GHz Active RFID Tag with On-Chip Antenna

This paper presents a fully integrated active RFID tag, realized in a 3.3V 0.35µm CMOS process, which exploits an on-chip loop antenna for short-range communications. This solution eliminates the need of a post-process assembled external antenna thus allowing to obtain a low-cost system for RFID applications. The implemented chip uses a 2.5GHz complementary cross-coupled LC oscillator based OOK transmitter. The system is duty cycled for reducing the power consumption. For the transmission of the stored 32bit indentifying code at 5kbit/s data rate, the average power consumption is 160µW. The integrated loop antenna radiates sufficient power for 1m communication range.

CMOS Fully Integrated 2 5GHz Active RFID Tag with On chip antenna PDF

A Universal UHF RFID Reader IC in 0.18-µm CMOS Technology (original) (raw)

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