An Functional Spiking Neuron Hardware Oriented Model (original) (raw)
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A functional spiking neuron hardware oriented model
Lecture Notes in Computer Science, 2003
In this paper we present a functional model of spiking neuron intended for hardware implementation. The model allows the design of speedand/or area-optimized architectures. Some features of biological spiking neurons are abstracted, while preserving the functionality of the network, in order to define an architecture easily implementable in hardware, mainly in field programmable gate arrays (FPGA). The model permits to optimize the architecture following area or speed criteria according to the application. In the same way, several parameters and features are optional, so as to allow more biologically plausible models by increasing the complexity and hardware requirements of the model. We present the results of three example applications performed to verify the computing capabilities of a simple instance of our model.
An Efficient Implementation of a Realistic Spiking Neuron Model on an FPGA
2010
Hardware implementations of spiking neuron models have been studied over the years mainly in researches focused on bio-inspired systems and computational neuroscience. This introduced considerable challenges for researchers particularly in terms of the requirements to realise a efficient embedded solution which may provide artificial devices adaptability and performance in real-time environment. Thus, programmable hardware was widely used as a model for the adaptable requirements of neural networks. From this perspective, this paper describes an efficient implementation of a realistic spiking neuron model on a Field Programmable Gate Array (FPGA). A network consisting of 10 Izhikevich's neurons was produced, in a low-cost and low-density FPGA. It operates 100 times faster than in real time, and the perspectives of these results in newer models of FPGAs are promising.
Comparative Investigation into Classical and Spiking Neuron Implementations on FPGAs
Lecture Notes in Computer Science, 2005
The current growth of neuron technology is reflected by the increasing focus on this research area within the European research community. One topic is the implementation of neural networks (NNs) onto silicon. FPGAs provide an excellent platform for such implementations. The development of NNs has led to multiple abstractions for various generations. The different demands that each generation pose, present different design challenges. This has left ambiguous decisions for the neuroengineer into what model to implement. The authors have undertaken an investigation into four commonly selected neuron models, two classical models and two formal spike models. A software classification problem is combined with hardware resource requirements for FPGAs, implemented utilising a novel design flow. This provides an overall comparative analysis to be made and identification of the most suitable model to implement on an FPGA.
2005
The implementation of a large scale, leaky-integrate-and-fire neural network processor using the Xilinx Virtex-II family of field programmable gate array (FPGA) is presented. The processor has been designed to model biologically plausible networks of spiking neurons in real-time to assist with the control of a mobile robot. The real-time constraint has led to a re-evaluation of some of the established architectural and algorithmic features of previous spiking neural network based hardware. The design was coded and simulated using Handel-C hardware description language (HDL) and the DK3 design suite from Celoxica. The processor has been physically implemented and tested on a RC200 development board, also from Celoxica.
An FPGA-based model suitable for evolution and development of spiking neural networks
2008
We propose a digital neuron model suitable for evolving and growing heterogeneous spiking neural networks on FPGAs using a piecewise linear approximation of the Quadratic Integrate and Fire (QIF) model. A network of 161 neurons and 1610 synapses with 4210 times realtime neuron simulation speed was simulated and synthesized for a Virtex-5 chip.
An FPGA Platform for Real-Time Simulation of Spiking Neuronal Networks
Frontiers in Neuroscience, 2017
In the last years, the idea to dynamically interface biological neurons with artificial ones has become more and more urgent. The reason is essentially due to the design of innovative neuroprostheses where biological cell assemblies of the brain can be substituted by artificial ones. For closed-loop experiments with biological neuronal networks interfaced with in silico modeled networks, several technological challenges need to be faced, from the low-level interfacing between the living tissue and the computational model to the implementation of the latter in a suitable form for real-time processing. Field programmable gate arrays (FPGAs) can improve flexibility when simple neuronal models are required, obtaining good accuracy, real-time performance, and the possibility to create a hybrid system without any custom hardware, just programming the hardware to achieve the required functionality. In this paper, this possibility is explored presenting a modular and efficient FPGA design of an in silico spiking neural network exploiting the Izhikevich model. The proposed system, prototypically implemented on a Xilinx Virtex 6 device, is able to simulate a fully connected network counting up to 1,440 neurons, in real-time, at a sampling rate of 10 kHz, which is reasonable for small to medium scale extra-cellular closed-loop experiments.
2008
We propose a digital neuron model suitable for evolving and growing heterogeneous spiking neural networks on FPGAs by introducing a novel flexible dendrite architecture and the new PLAQIF (Piecewise-Linear Approximation of Quadratic Integrate and Fire) soma model. A network of 161 neurons and 1610 synapses was simulated, implemented, and verified on a Virtex-5 chip with 4210 times real-time speed with 1 ms resolution. The parametric flexibility of the soma model was shown through a set of experiments.
FPGA Implementation of Spiking Neural Network
1st Conference on Embedded Systems, Computational Intelligence and Telematics in Control, 2012
ABSTRACT Spiking Neural Networks (SNN) have optimal characteristics for hardware implementation. They can communicate among neurons using spikes, which in terms of logic resources, means a single bit, reducing the logic occupation in a device. Additionally, SNN are similar in performance compared to other neural Artificial Neural Network (ANN) architectures such as Multilayer Perceptron, and others. SNN are very similar to those found in the biological neural system, having weights and delays as adjustable parameters. This work describes the chosen models for the implemented SNN: Spike Response Model (SRM) and temporal coding is used. FPGA implementation using VHDL language is also described, detailing logic resources usage and speed of operation for a simple pattern recognition problem.
FPGA Implementation of Simplified Spiking Neural Network
2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2020
Spiking Neural Networks (SNN) are thirdgeneration Artificial Neural Networks (ANN) which are close to the biological neural system. In recent years SNN has become popular in the area of robotics and embedded applications, therefore, it has become imperative to explore its real-time and energy-efficient implementations. SNNs are more powerful than their predecessors because they encode temporal information and use biologically plausible plasticity rules. In this paper, a simpler and computationally efficient SNN model using FPGA architecture is described. The proposed model is validated on a Xilinx Virtex 6 FPGA and analyzes a fully connected network which consists of 800 neurons and 12,544 synapses in real-time.
Design of the spiking neuron having learning capabilities based on FPGA circuits
3rd IFAC Workshop on Discrete-Event System Design (2006), 2006
Hardware real-time implementations of Spiking Neuron Networks (SNN) are wanted for multiple applications. Introduction of the supervised learning mechanism for SNNs is a hot topic. A model of a single spiking neuron having that property is proposed. This is based on LIF simplied model. A number of design issues has been solved in order to enable the correct work of such a neuron during learning phase. The proposed extensions and modications are described and illustrated with corresponding timing diagrams.