Toward Systematic Construction of Timing Diagrams from UML/MARTE Behavioral Models for Time-Triggered Embedded Software (original) (raw)
Related papers
Automatic construction of timing diagrams from UML/MARTE models for real-time embedded software
Proceedings of the 29th Annual ACM Symposium on Applied Computing, 2014
Analysis of timing constraints is an essential part in developing real-time embedded software. Performing the timing analysis during the early development phases prevents timing violations and enhances software quality. In the development of real-time embedded software, UML timing diagrams can play a significant role since they can provide not only intuitive specifications for timing constraints, but also valuable information for verifying system requirements. However, as software complexity increases, modeling timing diagrams is becoming difficult and costly. We propose an automated construction approach of timing diagrams from UML sequence diagrams and state machine diagrams with MARTE annotations. The proposed approach enables developers of RTES to save time required for modeling timing diagrams and prevents making mistakes in construction of timing diagrams.
Automated Analysis of Timing Information in UML Diagrams
2004
This paper introduces an approach to adding timing information to UML diagrams for modeling embedded systems. In order to perform automated formal analysis of these UML diagrams with timing information, we extend a previously developed UML formalization framework to provide Promela semantics for the timing elements of the UML diagrams. The paper describes the application of our approach to an electronically controlled steering system obtained from one of our industrial collaborators. § The authors are grateful for the feedback regarding this work and paper that we received from
Polychronous Analysis of Timing Constraints in UML MARTE
2010 13th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops, 2010
The UML Profile for Modeling and Analysis of Real-Time and Embedded systems (MARTE) defines a broadly expressive Time Model to provide a generic timed interpretation for UML models. As a part of MARTE, Clock Constraint Specification Language (CCSL) allows the specification of systems with multiple clock domains as well as nondeterminism. In this paper, we propose to take advantage of Polychrony clock calculus, named hierarchization, to analyze timed systems specified in CCSL, and to generate code for simulation considering determinism. Hierarchization enables to identify the endochrony property in a system that allows code generation ensuring determinism. The presented work is being integrated into the TimeSquare environment dedicated to the simulation of MARTE timed systems.
Modeling and Simulation of Timing Behavior with the Timing Definition Language
Computational Analysis, Synthesis, & Design Dynamic Systems, 2012
Most of the existing modeling methods and tools for embedded application development use levels of abstraction where execution and communication times of computational tasks are not adequately captured. Thus, properties such as time and value determinism, which are crucial for safety-critical real-time systems, cannot be guaranteed when refining the model to move it closer to a target platform. In many cases, the link between the abstract model and its implementation is broken during the refinement process. An additional problem is that the resulting software components are often not portable and composable. The Logical Execution Time (LET) abstraction has been proposed to deal with these issues and to offer a correct-by-construction development that formally guarantees time and value determinism and that delivers portable embedded software components. LET allows the explicit, platform-independent specification of execution times. This chapter deals with the modeling and simulation of safety-critical embedded applications where timing requirements are specified in the Timing Definition Language (TDL) which supports the LET abstraction. TDL provides a programming model for both the time-triggered paradigm and the event-triggered paradigm. TDL components can be automatically deployed to large-scale distributed systems. We present a selection of TDL constructs and sketch the 2 seamless integration of TDL with two simulation environments, the MATLAB ® /Simulink ® [31] products from MathWorks ® and the open-source Ptolemy framework from the University of California, Berkeley.
Polychronous modeling, analysis, verification and simulation for timed software architectures
2013
High-level modeling languages and standards, such as Simulink, SysML, MARTE and AADL (Architecture Analysis & Design Language), are increasingly adopted in the design of embedded systems so that system-level analysis, verification and validation (V&V) and architecture exploration are carried out as early as possible. This paper presents our main contribution in this aim by considering embedded systems architectural modeling in AADL and functional modeling in Simulink; an original clock-based timing analysis and validation of the overall system is achieved via a formal polychronous/multi-clock model of computation. In order to avoid semantics ambiguities of AADL and Simulink, their features related to real-time and logical time properties are first studied. We then endue them with a semantics in the polychronous model of computation. We use this model of computation to jointly analyze the non-functional real-time and logical-time properties of the system (by means of logical and affine clock relations). Our approach demonstrates, through several case-studies conducted with Airbus and C-S Toulouse in the European projects CESAR and OPEES, how to cope with the system-level timing verification and validation of high-level AADL and Simulink components in the framework of Polychrony, a synchronous modeling framework dedicated to the design of safety-critical embedded systems.
UML MARTE Time Model and Its Clock Constraint Specification Language
Handbook of Research on Embedded Systems Design, 2014
The UML Profile for MARTE extends the UML with constructs dedicated to the modeling and analysis of real-time and embedded systems. Its time profile provides a rich model of time based on the notion of logical clocks that can be used consistently through all modeling elements/diagrams. The MARTE time profile comes with a companion language, called CCSL. CCSL is a formal declarative language used to handle the MARTE logical clocks and schedule the execution of the different parts of a model. This chapter gives a snapshot on modeling and analysis facilities that have been developed specifically around the time profile of MARTE and CCSL. A second objective is to show how MARTE can be combined with other profiles such as EAST-ADL. The last objective is the use of CCSL as a common language for specifying the semantics of models to allow their execution in a common framework. The MARTE and EAST-ADL constructs are illustrated on an example of a simplified cruise control. The example starts with a description of functional and timing requirements captured using a specific profile called EAST-ADL dedicated to the automotive domain. Then some of the requirements are refined with UML state machines and activities adorned with MARTE stereotypes. All these models rely on MARTE clocks. The semantics of these diagrams is given by a CCSL description that is automatically derived from the models. The resulting CCSL specification can be used to execute the UML/EAST-ADL specification, to animate the model, or to perform various kinds of analyses.
UML based design of time triggered systems
Seventh IEEE International Symposium onObject-Oriented Real-Time Distributed Computing, 2004. Proceedings., 2004
This paper presents how the platform-specific development environment of time-triggered (TT) systems can be integrated with a visual design toolkit based on UML. The built-in facilities of UML and the modeling extensions introduced by us enable the unification of the advantages provided by both the embedded development environment and the UML tools. UML offers visual design, automatic code and documentation generation, while the underlying TT development environment offers platform-specific task and communication scheduling and fault tolerance middleware construction. This results in an integrated system that is capable of supporting the entire development within the framework of the UML tool.
components F lightP lan and Database respectively through ports plan and param). If so, the Database component notifies T rajectory that the new parameters values need to be taken into account (their respective ports param are connected). The parameters are stored in the cache of T rajectory, in their arrival order (see the MARTE annotation dataP ool stating that data is inserted/consumed in a FIFO oder). When computations are completed, T rajectory generates navigation commands transmitted (through a dedicated port navCmd) to external equipment.
Modeling with Logical Time in Uml for Real-Time Embedded System Design
2000
ABSTRACT: Design of real-time embedded,systems requires particular attention to the careful scheduling of application onto execution platform. Precise cycle allocation is often requested to obtain full communication,and computation throughput. Our objective is to provide a UML prole where events, actions, and objects can be annotated by ìlogicalî clocks. Initially, clocks are not necessarily related. The goal of the scheduling process