High-Speed Unified Elliptic Curve Cryptosystem on FPGAs Using Binary Huff Curves (original) (raw)
Related papers
A Unified Point Multiplication Architecture of Weierstrass, Edward and Huff Elliptic Curves on FPGA
Applied Sciences, 2023
This article presents an area-aware unified hardware accelerator of Weierstrass, Edward, and Huff curves over � � ( 2 233 ) for the point multiplication step in elliptic curve cryptography (ECC). The target implementation platform is a field-programmable gate array (FPGA). In order to explore the design space between processing time and various protection levels, this work employs two different point multiplication algorithms. The first is the Montgomery point multiplication algorithm for the Weierstrass and Edward curves. The second is the Double and Add algorithm for the Binary Huff curve. The area complexity is reduced by efficiently replacing storage elements that result in a 1.93 times decrease in the size of the memory needed. An efficient Karatsuba modular multiplier hardware accelerator is implemented to compute polynomial multiplications. We utilized the square arithmetic unit after the Karatsuba multiplier to execute the quad-block variant of a modular inversion, which preserves lower hardware resources and also reduces clock cycles. Finally, to support three different curves, an efficient controller is implemented. Our unified architecture can operate at a maximum of 294 MHz and utilizes 7423 slices on Virtex-7 FPGA. It takes less computation time than most recent state-of-the-art implementations. Thus, combining different security curves (Weierstrass, Edward, and Huff) in a single design is practical for applications that demand different reliability/security levels.
Fpga Implementations of High Speed Elliptic Curve Cryptography: A Survey
ijser.org
An explosi ve acceptance of Elliptic Curve Cryptography (ECC) has been attained in the industry and academics. Elliptic Curve cryptography i s an approach to public-key cryptography based on the algebrai c structure of elliptic curves over finite fields. The ECC is advantageous due to the provision of high level of security and the usage of small keys. In the field of Mobile, Wireless and Network servers, to sustain the high throughput the implementations of high speed crypto-systems are needed. ECC has been extensivel y used for hardware implementation of FPGA and DedicatedASIC. This paper attempts to conduct a detailed survey on di fferent techniques for implementing FPGA using ECC to achieve high speed and flexibility.
WSEAS Transactions on Computers, 2009
Embedded systems find applications in fields such as defense, communications, industrial automation and many more. For majority of these applications, security is a vital issue. Over the last decade, security has become the primary concern when discussing e-commerce. The rapid development in the field of information technology has led to the increase in need of techniques capable of providing security. Cryptography plays an important role in providing data security. Until recently, symmetric key encryption schemes were used for a majority of these applications. Now however, asymmetric key encryption schemes such as Elliptic curve cryptography are gaining popularity as they require less computational power and memory and are still capable of providing equivalent security when compared to their counterparts. Elliptic curve cryptography was first introduced in 1985 and has always been around since. Scalar or point multiplication in elliptic curve cryptography has been a topic of research interest. Improving the performance of scalar multiplication can improve the overall performance of elliptic curve cryptography. One popular method to improve scalar multiplication is by means of hardware accelerators. The authors of this paper have implemented scalar multiplication, the most time consuming operation in elliptic curve cryptography using binary non-adjacent form algorithm. The results of the software implementation have been presented in section-4. Methodology to improve the performance of the scalar multiplication by use of hardware accelerators has also been presented in this paper.
A hardware analysis of Twisted Edwards curves for an elliptic curve cryptosystem
… , Tools and Applications, 2009
This paper presents implementation results of a reconfigurable elliptic curve processor defined over prime fields GF (p). We use this processor to compare a new algorithm for point addition and point doubling operations on the twisted Edwards curves, against a current standard algorithm in use, namely the Double-and-Add. Secure power analysis versions of both algorithms are also examined and compared. The algorithms are implemented on an FPGA, and the speed, area and power performance of each are then evaluated for various modes of circuit operation using parallel processing. To the authors' knowledge, this work introduces the first documented FPGA implementation for computations on twisted Edwards curves over fields GF (p).
FPGA based hardware acceleration for elliptic curve public key cryptosystems
Journal of Systems and Software, 2004
trations (E-Government) give rise to the important question, how to reliably exchange confidential data via public communication networks such as the Internet. Any data transfer must be protected from a fraudulent access by third parties in the sense that it has to be ensured that exchanged documents are neither read nor modified during the data transfer. Furthermore, the author-document relationships have to be known and unique at any point in time. The fundamental technology for document protection during public data transfer is known as public key cryptography. Digital signature schemes are probably the most common occurrence of public key cryptosystems. This paper addresses public key cryptosystems based on elliptic curves, which are aimed to high-performance digital signature schemes. Elliptic curve (EC) algorithms are characterized by the fact that one can work with considerably shorter keys compared to the RSA approach at the same level of security. A general and highly efficient method for mapping the most time-critical operations to a configurable co-processor is proposed. By means of real-time measurements the resulting performance values are compared to previously published state of the art hardware im-
Enhanced FPGA Implementations for Doubling Oriented and Jacobi-Quartics Elliptic Curves Cryptography
2011
The rapid advances in communication networks impose the fact of transferring big amounts of information worldwide every second. Considerable part of this information might need protection against fraud, modification and different types of intrusion. Both, the symmetric and asymmetric encryption algorithms provide different types of security services to protect sensitive information. Lately, the National Institute of Standards and Technology issued Federal Information Processing Standards to direct the researcher’s attention to the asymmetric cryptographic algorithms based on elliptic curves. In this paper, algorithms and design issues related to two new curves: Doubling Oriented, and Jacobi-Quartics, are proposed and analyzed. Then, different implementation approaches are studied and applied for the different curves. Experimental results are provided to show the enhancements on the execution delay and the total design area of the proposed FPGA realizations.
An Efficient Crypto Processor Architecture for Side-Channel Resistant Binary Huff Curves on FPGA
Electronics
This article presents an efficient crypto processor architecture for point multiplication acceleration of side-channel secured Binary Huff Curves (BHC) on FPGA (field-programmable gate array) over GF(2233). We have implemented six finite field polynomial multiplication architectures, i.e., (1) schoolbook, (2) hybrid Karatsuba, (3) 2-way-karatsuba, (4) 3-way-toom-cook, (5) 4-way-toom-cook and (6) digit-parallel-least-significant. For performance evaluation, each implemented polynomial multiplier is integrated with the proposed BHC architecture. Verilog HDL is used for the implementation of all the polynomial multipliers. Moreover, the Xilinx ISE design suite tool is employed as an underlying simulation platform. The implementation results are presented on Xilinx Virtex-6 FPGA devices. The achieved results show that the integration of a hybrid Karatsuba multiplier with the proposed BHC architecture results in lower hardware resources. Similarly, the use of a least-significant-digit-pa...
An Elliptic Curve Cryptosystem Design Based on FPGA Pipeline Folding
13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
In this paper we present an efficient design technique for implementing the Elliptic Curve Cryptographic (ECC) Scheme in FPGAs. Our technique is based on a novel and efficient implementation of modular multiplication which is the core operation of ECC. To implement large bit-length multiplications we used a novel partitioning and pipeline folding scheme to fit at least 256-bit modular multiplications on a single Virtex-4 FPGA. Comparisons to several other schemes are presented.
On the hardware design of an elliptic curve cryptosystem
Proceedings of the Fifth Mexican International Conference in Computer Science, 2004. ENC 2004., 2004
We present a hardware architecture for an Elliptic Curve Cryptography System performing the three basic cryptographic schemes: DH key generation, encryption and digital signature. The architecture is described by using hardware description languages, specifically Handel C and VHDL. Because of the sequential nature of the cryptographic algorithms, they are written in Handel C language. The critical part of the cryptosystem is a module performing the scalar multiplication operation. This module has been written in VHDL to let further improvements. The points of the elliptic curve are represented in projective coordinates working over the two-characteristic finite field and using polynomial basis. A prototype of this hardware architecture is implemented on a Xilinx Virtex II FPGA device.
Coupled FPGA/ASIC Implementation of Elliptic Curve Crypto-Processor
International Journal of Network Security & Its Applications, 2010
In this paper, we propose an elliptic curve key generation processor over GF scheme based on the Montgomery scalar multiplication algorithm. The new architecture is performed using polynomial basis. The Finite Field operations use a cellular automata multiplier and Fermat algorithm for inversion. For real time implementation, the architecture has been tested on an ISE 9.1 Software using Xilinx Virtex II Pro FPGA and on an ASIC CMOS 45 nm technology as well. The proposed implementation provides a time of 2.07 ms and 38 percent of Slices in Xilinx Virtex II Pro FPGA. Such features reveal the high efficiently of this implementation design.