Exploiting Syntactic Structure for Automatic Verification (original) (raw)

Test sequence generation and model checking using dynamic transition relations

International Journal on Software Tools for Technology Transfer, 2004

The task of finding a set of test sequences that provides good coverage of industrial circuits is infeasible because of the size of the circuits. For small critical subcircuits of the design, however, designers can create a set of test sequences that achieve good coverage. These sequences cannot be used on the full design because the inputs to the subcircuit may not be accessible. In this work we present an efficient test generation algorithm that receives a test sequence created for the subcircuit and finds a test sequence for the full design that reproduces the given sequence on the subcircuit. The algorithm uses a new technique called dynamic transition relations to increase its efficiency. The most common and most expensive step in our algorithm is the computation of the set of predecessors of a set of states. To make this computation more efficient we exploit a partitioning of the transition relation into a set of simpler relations. At every step we use only those that are necessary, resulting in a smaller relation than the original one. A different relation is used for each step, hence the name dynamic transition relations. The same idea can be used to improve symbolic model checking for the temporal logic CTL. We have implemented the new method in SMV and run it on several large circuits. Our experiments indicate that the new method can provide gains of up to two orders of magnitude in time and space during verification. These results show that dynamic transition relations can make it possible to verify circuits that were previously unmanageable due to their size and complexity.

Combining Software and Hardware Verification Techniques

Formal Methods in System Design, 2002

Combining verification methods developed separately for software and hardware is motivated by the industry's need for a technology that would make formal verification of realistic software/hardware co-designs practical. We focus on techniques that have proved successful in each of the two domains: BDD-based symbolic model checking for hardware verification and partial order reduction for the verification of concurrent software programs. In this paper, we first suggest a modification of partial order reduction, allowing its combination with any BDD-based verification tool, and then describe a co-verification methodology developed using these techniques jointly. Our experimental results demonstrate the efficiency of this combined verification technique, and suggest that for moderate-size systems the method is ready for industrial application.

Using a hardware model checker to verify software

ASIC, 2001. Proceedings. 4th …, 2001

A variety of new algorithms has begun to enable model checking of industrial-sized netlists. This work attempts to apply that technology to the verification of embedded software: C programs that manipulate integers and contain unstructured control flow, but are not recursive and do not dynamically allocate memory.

Hardware Verification Using Software Analyzers

2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Program analysis is a highly active area of research, and the capacity and precision of software analyzers is improving rapidly. We investigate the use of modern software verification tools for formal property checking of hardware given in Verilog at register-transfer level. To this end, we translate RTL Verilog into an equivalent word-level ANSI-C program, according to synthesis semantics. The property of interest is instrumented into the C program as an assertion. We subsequently apply three different software verification techniques-bounded model checking, path-based symbolic simulation and abstract interpretationand compare their performance to conventional methods for property verification of hardware designs at netlist and registertransfer level. Our experimental results indicate that speedups of more than an order of magnitude are possible. To the best of our knowledge, this is the first attempt to perform property verification of hardware IPs given at register-transfer level using software verifiers.

Efficient model checking by automated ordering of transition relation partitions

Lecture Notes in Computer Science, 1994

In symbolic model checking, the behavior of a model to be verified is captured by the transition relation of the state space implied by the model. Unfortunately, the size of the transition relation grows rapidly with the number of states even for small models, rendering them impossible to verify. A recent work [5] described a method for partitioning the transition relation, thus reducing the overall space requirement. Using this method, actions that require the transition relation can be executed by using one partition at a time. This process, however, strongly depends on the order in which the partitions are processed during the action.

Application of Model Checking to the Verification of Digital Systems

2009

The article presented here deals with the verification of a digital design using temporal logic and model checking. Temporal logic has been used as a specification language to catch the behaviour of the system design and model checking has been chosen as a verification method to evaluate the design accuracy. As a digital system to be modelled and verified we have chosen the sequence detector; the detected string is 010. To compare the way how to establish temporal model and its properties and to see better coincidences and differences in describing their behaviour we made up the model of the sequence detector in two variants: without and with overlapping. We took, as finite state machine (FSM), the both automata, the Moore as well as the Mealy, each considered without and with overlapping. After the temporal properties of the four drawn models had been defined we wrote respective programs corresponding to each of models, in SMV language, to pass them as input files into the SMV mode...

Verification of hardware descriptions by retargetable code generation

Proceedings of the 1989 26th ACM/IEEE conference on Design automation conference - DAC '89, 1989

This paper 1 proposes a new method for hardware veri cation. The basic idea is the application of a retargetable compiler as veri cation tool. A retargetable compiler is able to compile programs into the machine code of a speci ed hardware target. If the program is the complete behavioural speci cation of the target, the compiler can be used to verify that a properly programmed structure implements the behaviour. Methods, algorithms and applications of an existing retargetable compiler are described.

A methodology for processor implementation verification

Lecture Notes in Computer Science, 1996

We address the problem of verification of implementations of complex processors using architectural level automatic test program generators. A number of automatic test program generators exist, and are widely used for verification of the compliance of complex processors with their architectures. We define a four stage verification process: (1) describing the processor implementation control as a Finite State Machine (2) deriving transition coverage on the FSM using methods from formal verification (3) translation of the covering tours to constraints on test programs (4) generation of test programs for each set of constraints. This process combines a high quality and well defined theoretical method along with tools used in industrial practice. There are a number of advantages of our Method: (a) The last three stages are automated (b) Implementing the FSM model involves relatively little expert designers time (c) The method is feasible for modern superscalar processors and was studied on an enhanced PowerPC processor. We describe a formal framework for the new process, identify the obstacles that are encountered in the modeling phase, and show how to overcome them.

Logic design verification via test generation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988

This paper describes a new method for logic design verification in which a gate-level implementation of a circuit is compared with a functional-level specification. In this method, test patterns, developed to detect single stuck-line faults in the gate-level implementation, are used instead to compare the gate-level implementation with the functional-level specification. In the presence of certain hypothesized design errors, such a test set will produce responses in the implementation that disagree with the responses in the specification. It is shown that the class of design errors that can be detected in this way is very large.