Interval Arithmetic Multiplier for Digital Signal Processors (original) (raw)

Interval Arithmetic Logic Unit for DSP and Control Applications

2006

GUPTE, RUCHIR. Interval Arithmetic Logic Unit for DSP and Control Applications. (Under the direction of Prof. William W. Edmonson). There are many applications in the field of digital signal processing (DSP) and controls that require the user to know how various numerical errors (uncertainty) affect the result. Interval Arithmetic (IA) eliminates this uncertainty by replacing non-interval values with intervals. Since most DSPs operate in real time environments, fast processors are needed. The goal is to develop a platform in which interval arithmetic operations are performed at the same computational speed as present day signal processors. This thesis proposes a design for an interval based arithmetic logic unit (I-ALU) whose computational time for implementing interval arithmetic operations is equivalent to many digital signal processors. Many DSP and control applications require a small subset of arithmetic operations that must be computed efficiently. This design has two independ...

Interval Arithmetic Logic Unit for Signal Processing and Control Applications

2006

There are many applications within digital signal processing (DSP) and controls that require the user to know how various numerical errors aect the result, i.e. uncertainty. This uncertainty is represented by replacing non-interval values with intervals. Since most DSPs operate in real time environments, fast processors are needed. The goal is to develop a platform in which interval arithmetic operations are performed at the same computational speed as present day signal processors. We have proposed a design for an interval based arithmetic logic unit (I-ALU) whose computational time for implementing interval arithmetic operations is equivalent to many digital signal processors. Many DSP and control applications require a small subset of arithmetic operations that must be computed eciently. This design has two independent modules operating in parallel to calculate the lower bound and upper bound of the output interval. The functional unit of the ALU performs the basic fixed-point in...

Design of optimized Interval Arithmetic Multiplier

2018

Many DSP and Control applications that require the user to know how various numerical errors(uncertainty) affect the result. This uncertainty is eliminated by replacing non-interval values with intervals. Since most DSPs operate in real time environments, fast processors are required to implement interval arithmetic. The goal is to develop a platform in which Interval Arithmetic operations are performed at the same computational speed as present day signal processors. So we have proposed the design and implementation of Interval Arithmetic multiplier, which operates with IEEE 754 numbers. The proposed unit consists of a floating point CSD multiplier, Interval operation selector. This architecture implements an algorithm which is faster than conventional algorithm of Interval multiplier . The cost overhead of the proposed unit is 30% with respect to a conventional floating point multiplier. The performance of proposed architecture is better than that of a conventional CSD floating-po...

Basic concepts of interval digital signal processing

Interval mathematics has been used in Signal Processing as a tool for representing uncertainties that arise from finite numeric representation, limited precision sensors and the quantization process. In some control systems, such as soft computing or forecast systems, the uncertainties are a consequence of variable instability, signal variance, or the safety rate of some actuators. Papers with specific applications in this area have been published, but few have dealt with the theoretical foundation of interval mathematics applied to signal processing. This essay is a starting point on interval mathematics in the foundation of signal processing. It is an analytical approach for dealing with interval linear systems with an application perspective in signal processing. Interval linear systems will be used as mathematical models in real systems representation, where the intervals represent the uncertainty of the system. In this approach only linear and time invariant systems with single input and single output (SISO) are used. For this purpose the classical basic properties of real linear systems will be extended. These properties are: causality, stability, additivity and homogeneity. Finally, an interval convolution definition is proposed to represent uncertainty systems and signals more accurately; it is also an important tool for digital signal processing.

Efficient 16-bit floating-point interval processor for embedded systems and applications

2006

Abstract This paper presents the implementation of a 16-bit interval floating-point unit on a soft-core processor to allow interval computations for embedded systems. The distributed localization of a source using a network of sensors is presented to compare the performance of the proposed processor to those obtained with a general-purpose processor.

Design of floating point units for interval arithmetic

2009

Interval arithmetic has been proven a more reliable alternative to the conventional floating point arithmetic. A great number of mathematical methods that use interval arithmetic with applicability in a wide range of fields, like computer graphics, air traffic control, physics, have been developed. However, these methods are slow and inefficient on modern computers due to the lack of hardware support. Therefore, the main goal of this thesis is to design floating point units suitable for interval arithmetic, in order to exploit the full potential of interval methods. The designed units have to be similar in cost and performance with respect to conventional floating point units. Furthermore, because interval arithmetic is not meant to be a replacement of the conventional floating point arithmetic, but an extension of it, the proposed units have also to be suitable for conventional floating point arithmetic. Other approaches consisted on developing hardware support for interval arithmetic by incorporating existing conventional floating point units. My approach relies on the design of these units from almost zero, by taking into account algorithms for interval operations and the particularities for each floating point operation (normalization, rounding algorithms, exponent computation, etc). A very important aspect of the research is the analysis of the proposed circuits in terms of cost and performance. The cost will be estimated in terms of gate count. The performance will be estimated both in the latency of the circuits (measured in logic levels) and by estimating the performance of different interval methods on the proposed units. Thus, a benchmark type analysis is required. Because in interval arithmetic there is no known set of benchmarks programs (similar to SPEC-FPU), a benchmark proposal will also be made in this thesis.

A family of variable-precision interval arithmetic processors

IEEE Transactions on Computers, 2000

AbstractÐTraditional computer systems often suffer from roundoff error and catastrophic cancellation in floating point computations. These systems produce apparently high precision results with little or no indication of the accuracy. This paper presents hardware designs, arithmetic algorithms, and software support for a family of variable-precision, interval arithmetic processors. These processors give the programmer the ability to detect and, if desired, to correct implicit errors in finite precision numerical computations. They also provide the ability to solve problems that cannot be solved efficiently using traditional floating point computations. Execution time estimates indicate that these processors are two to three orders of magnitude faster than software packages that provide similar functionality.

A Fast Multiplier Hardware Design for Interval Arithmetic

Istanbul University - Journal of Electrical and Electronics Engineering, 2006

In this paper, a new parallel hardware unit for interval multiplication is presented. Using the VHDL synthesis results, the area and delay estimates for the new design are given. Compared to previous hardware interval multipliers, our design is faster, but, requires more area.

FFT based Interval Arithmetic Analysis for Signal Processing System

Journal of emerging technologies and innovative research, 2020

Signal processing is become a dominant role in the area of engineering. Very large scale integration made a rapid advance in the research area of Digital Signal Processing in terms of high speed VLSI architecture for real time applications. DFT is one of the important operations in digital signal processing. DFT converts a signal in discrete time domain to discrete frequency domain. Fast Fourier Transform (FFT) is a form of DFT. It is used in reducing the complexity of computations. We propose interval arithmetic CORDIC architectures to efficiently support and identify the accuracy to accomplish interval trigonometric functions, to guarantee the correct possible option of the bounds of the final value with minimum error, to analyze and to measure signals for the use of DSP (Digital signal processing) applications. This paper presents interval arithmetic Cordic algorithm based FFT for improvement in performance and signal processing implementation using MATLAB toolbox INTLAB. Interva...

Interval Arithmetic. A practical implementation

2015

You can find example of interval arithmetic template class for the C++ programming language but none that is easy to understand and easy to implement and that is the reason why this paper was written. The paper highlights the implementation of a general interval template class supporting the float and double type of the C++ programming language. Building an interval template software class that can handle all interval arithmetic for IEEE754 floating point is just down to simple math. This paper describe the practical implementation aspect of building an interval template class and discuss the tricks and math that is behind the implementation. The implementation spans from the basic