Variable-Voltage Class-E Power Amplifiers (original) (raw)
Design Procedure of Quasi-Class-E Power Amplifier for Low-Breakdown-Voltage Devices
IEEE Transactions on Circuits and Systems I-regular Papers, 2014
This paper presents new design procedure for a general class-E power amplifier, here referred to as quasi-class-E, with finite dc-feed inductance and switch on-resistance and variable duty cycle under variable voltage switching (VVS), and variable derivative voltage switching (VDS), taking into account the switch breakdown voltage. It is shown that for non-zero switch on-resistance in class-E power amplifier, zero voltage switching (ZVS) and zero derivative switching (ZDS) conditions do not necessarily result in maximum efficiency. Hence, by assuming VVS and VDS, new design equations are derived. The new equations can be solved with a simple and fast numerical method in MATLAB. The theoretical results show efficiency improvement for quasi-class-E power amplifier compared to conventional designs. Circuit simulations confirm the validity of the theoretical results. Index Terms-Any duty cycle, finite dc-feed inductance, quasiclass-E power amplifier, switch on-resistance, variable derivative voltage switching (VDS), variable voltage switching (VVS).
Design of Class E Power Amplifier with New Structure and Flat Top Switch Voltage Waveform
IEEE Transactions on Power Electronics, 2018
In this paper, a new topology of the class E power amplifier (PA) is proposed. The output circuit in the proposed power amplifier is different from that in the conventional class E PA. The conventional output circuit of class E power amplifier consists of shunt capacitor, resonant capacitor, resonant inductor, and shifting inductor. An additional shunt capacitance is added between the resonant capacitance and the shifting inductor to shape the reduced switch voltage. The peak switch voltage of the proposed class E PA is approximately 78% of that of the conventional one, which shows a reduction in peak switch voltage. The lower peak switch voltage reduces the breakdown voltage of the active device. Also, the proposed structure can introduce a new family of switching power amplifiers with interesting specifications. Several values of switch voltage reduction and output power capability could be achieved by varying the circuit elements. Zero voltage and zero derivative switching (ZVS and ZDS) conditions are achieved in the switch voltage of the designed circuit. The simulation of the proposed circuit is performed using PSpice software. For verification, the presented PA is fabricated and measured.
A Class e Power Amplifier with Low Voltage Stress
2015
A new output structure for class E power amplifier (PA) is proposed in this paper. A series LC resonator circuit, tuned near the second harmonic of the operating frequency is added to the output circuit. This resonator causes low impedance at the second harmonic. The output circuit is designed to shape the switch voltage of the class E amplifier and lower the voltage stress of the transistor. The maximum switch voltage of the conventional class E PA is 3.56Vdc. However, higher switch voltage of about 4.5VDC may be occurred, by considering nonlinear drain-to-source capacitance in class E PA. The obtained peak switch voltage of the designed class E PA is approximately 75% of the conventional one with the same conditions, which shows a significant reduction in peak switch voltage. MOSFET parasitic nonlinear gate-to-drain and nonlinear drain-to-source capacitances of the MOSFET body junction diode also affect the switch voltage in class E PA, which are considered in this paper. The actu...
IET Circuits, Devices & Systems, 2016
In this study, design theory and analysis for the class E power amplifier (PA), considering the metal oxide semiconductor field effect transistor (MOSFET) parasitic input and output capacitances, are proposed. The input resistance and capacitances cause non-ideal input voltage at gate terminal, which affect the specifications of the class E PA. In the proposed study, non-linear drain-to-source, linear gate-to-drain and linear gate-to-source MOSFET parasitic capacitances are considered, while zero voltage and zero derivative switching conditions are achieved. Moreover, the input resistance and the value of the input voltage are taken into account in the design theory. According to the obtained results, the duty cycle of the MOSFET depends on the MOSFET threshold voltage, input voltage, input series resistance, and some other parameters, which will be explained in this study. A design example is finally given to describe the design procedure at 1 MHz operating frequency along with the experimental result. The circuit simulation is also performed using PSpice software. The measured results showed quantitative agreements with simulation and theory results.
Analytical Design Equations for Class-E Power Amplifiers
IEEE Transactions on Circuits and Systems I-regular Papers, 2007
Many critical design trade-offs of the Class-E power amplifier (e.g power efficiency) are influenced by the switch onresistance and the value of dc-feed drain inductance. In literature, the time-domain mathematical analyses of the Class-E power amplifier with finite dc-feed inductance assume zero switch onresistance in order to alleviate the mathematical difficulties; resulting in non-optimum designs.
Efficient class-E power amplifier for variable load operation
2017 Integrated Nonlinear Microwave and Millimetre-wave Circuits Workshop (INMMiC), 2017
In this paper, a GaN HEMT class-E power amplifier (PA) has been designed for efficiently operating under variable load resistance at the 750 MHz frequency band. The desired zero voltage switching (ZVS) of the device can be approximated for a wide range of resistive loads, by means of a simple inductive impedance inverter, derived from [1]. The loadpull contours, obtained from simulations, allowed the drain terminating network to be properly adjusted in order to maximize the output power control while at the same time minimizing losses. Once the amplifier was implemented, an efficiency over 76% has been measured at 9.6 dB power back-off, with a peak of 85% at 50 Ω. In addition, the efficiency stays as high as 75% for a 150 MHz frequency range.
Analysis and design of class-E power amplifier considering MOSFET nonlinear capacitance
International Journal of Power Electronics and Drive Systems (IJPEDS), 2021
Class-E power amplifiers are integrated into many applications because their simple design and high performance. The efficiency of the power amplifier is significantly impacted by the nonlinear characteristic of the switching device, which is not analyzed clearly in theory. The nonlinear drain-tosource parasitic capacitance of the power transistor and the linear external capacitance are both contributed to the optimum conditions for obtaining the exact shunt capacitance. In this paper, a high-efficiency class-E power amplifier with shunt capacitance is designed with the consideration of both linear and nonlinear capacitance. Furthermore, a mathematical analysis is derived to calculate the component values in order to design the class-E power amplifier. Consequently, high power-added efficiency of 94.6% is obtained using MRF9030 MOSFET transistor with parameter of 4W output power and 13.56 MHz operating frequency. Finally, the measurement result of a linear class-E power amplifier circuit is obtained to compare and realize the efficiency of the proposed work.
Switch-Mode class-E Power amplifiers: a contribution toward high performance and reliability
2020
The increasing demands for high data rate necessitate the use of complex modulation schemes that require highly linear transmitters to optimize both the signal quality and the bandwidth usage. These two metrics are usually expressed in terms of error vector magnitude (EVM) and adjacent channel leakage ratio (ACLR). The power amplifiers (PAs), being the last active building block in a transmitter chain, greatly affect the signal quality. Also, typically, PAs are the most power hungry block that have a significant impact on the overall efficiency of a transmitter. Switch-mode class-E PAs have shown great potential for power efficient amplification of RF signals. Under certain conditions for the transistor voltage and current waveforms, this class of PAs provide (ideally) 100% efficiency. Also, due to the switched-mode operation of the transistors, class-E PAs are CMOS-friendly and show only a weak dependency on process variations. However, due to incorporating two tuned tanks, the dependency on the load impedance is relatively large, resulting in e.g. load dependent output power, power efficiency, peak voltages and peak (and average) currents which can lead to reliability issues. Load-mismatch can be due to (unintended) changes in the antenna environment or can be due to (intended) load modulation as with e.g. outphasing systems. This thesis work aims at high performance and reliable class-E PA. The first part of this thesis presents load pull analyses for class-E RF power amplifiers from a mathematical perspective, with analyses and discussions of the effects of the most common non-idealities of class-E PAs. This includes the limited loaded quality factor (Q loaded) of the series filter, switch on-resistance, limited quality factor of the DC-feed inductor, load mismatch dependent switch conduction loss and the limited negative voltage excursions (due to e.g. the reverse conduction of the switch transistor for negative voltage excursions). The theoretical findings are backed up by extensive circuit simulations and load pull measurements of a class-E power amplifier implemented in 65nm CMOS technology. Due to switch-mode operation, a single class-E with constant supply only allows phase modulation or On-Off Keying (OOK) modulation. One may use load modulation through outphasing to also enable amplitude modulation. The second part i Abstract of this thesis presents an analysis of outphasing class-E Power Amplifiers (OEPAs), using load-pull analyses of single class-E PAs. This analysis led to an approach that allows to rotate and shift power contours and rotate the efficiency contours to improve the efficiency of OEPAs at deep power back-off, to improve the Output Power Dynamic Range (OPDR) and to reduce switch voltage stress. The theory was validated using a 65nm CMOS demonstration that includes a pcb transmission-line based power combiner. OEPAs using isolating power combiners and an inverse cosine signal component separator are inherently linear but suffer from low efficiency at power back-off. For high efficiency both at maximum output power and at power back-off, non-isolating power combiners are required. In the third part of this thesis the linearity of OEPAs using non-isolating power combiners is studied theoretically and validated by measurement of an OEPA implemented in a standard 65nm CMOS technology using an off-chip transmission-line based combiner. The developed theoretical model for the linearity is then employed to define digital pre-distortion (DPD) parameters for the implemented OEPA. Using this theory-based DPD and without any AM/AM and AM/PM characterizations, the implemented OEPA provides a competitive linearity performance compared to the state of the art OEPAs.-31dB RMS EVM level and below-30dB ACLR were measured for a 13.1dBm 6.25MHz 30Mbit/s 7dB PAPR 64QAM signal with 41.8% drain efficiency and 33.6% power added efficiency. Finally, this thesis introduces a technique to self-protect/self-heal Class-E PAs against the effects of load variations, with only a minor impact on output power and efficiency. To validate the proposed technique, load-pull measurements are conducted on a class-E PA implemented in a standard 65nm CMOS technology, employing an offchip matching network, augmented with a fully automated self-protective/self-healing control loop. It is shown that the proposed self-protective PA can reduce its peak switch voltage from 5.4×V DD to below 3.8×V DD for all load mismatch conditions with VSWR up to 19:1 while output power and efficiency are not considerably affected. This allows to reduce the class-E PA's design margins significantly and to choose a higher V DD (to have a higher output power) compared to the case that the selfprotective control loop is disabled. The designed self-protective class-E PA provides 17.5dBm measured output power from a 1.2V supply under nominal load conditions (when all the losses of the matching network are included) and the switch voltage is always below the value allowed by the technology for all load mismatch conditions with VSWR up to 19:1. Overall, this thesis contributes to design of high performance and reliable switchmode class-E PAs. ii Dit maakt zowel een reductie in de benodigde ontwerpmarges van klasse-E PAs mogelijk, alsmede een verhoging van de voedingsspanning (met bijbehorende uitgangsvermogenverhoging). De ontworpen zelf-beschermende klasse-E eindversterker levert (gemeten) 17.5dBm uitgangsvermogen uit een 1.2V voeding onder nominale condities (waarbij het vermogensverlies van het matching-netwerk is inbegrepen) terwijl de schakelaarsspanning voor alle belastingsimpedantieomstandigheden met een VSWR tot 19:1 lager blijft dan de door de technologie maximaal toegestane waarde. Met deze innovaties levert het werk dat beschreven is in deze thesis een bijdrage aan het ontwerp van hoogwaardige en betrouwbare schakelende klasse-E eindversterkers voor radiofrequente toepassingen.
IEEE Transactions on Circuits and Systems I: Regular Papers, 2014
This paper presents analytical expressions for the sub-nominal operation, which is only the zero current switching (ZCS) condition, of the class-E power amplifier with a shunt inductor at any duty ratio. The duty ratio is considered not only as a design specification but also as an adjustment parameter. In the sub-nominal operation with any duty ratio, both the peak switch voltage and the peak switch current can be set as design specifications due to two more degrees of design freedom in comparison with the class-E nominal amplifier at the fixed duty ratio. Additionally, it is also seen that the duty ratio affects the maximum operating frequency and the output power capability with ZCS condition. A design example of the class-E ZCS amplifier with a shunt inductor under the specifications of peak switch voltage and peak switch current is given. The measurement and a simulation by circuit simulator results agreed with the analytical expressions quantitatively, which show the validity of our analytical expressions. Index Terms-Class-E power amplifier, duty ratio, maximum operating frequency, peak switch current, peak switch voltage, power conversion efficiency, shunt inductor, sub-nominal operation, zero-current switching (ZCS). I. INTRODUCTION T HE class-E power amplifier has two main operating modes, which are the nominal and the sub-nominal operation modes. The location of the class-E nominal conditions or the class-E sub-nominal condition [1]-[26] is directly determined by the duty ratio. Zero-voltage switching (ZVS) and zero-derivative voltage switching (ZDVS) are the nominal conditions for the class-E power amplifier with a shunt capacitance [1]-[9]. Similarly, zero-current switching (ZCS) and zero-derivative current switching (ZDCS) are the nominal conditions for the class-E power amplifier with a shunt inductor [10]-[13]. On the other hand, the sub-nominal condition means Manuscript