ATLAS pixel detector electronics and sensors (original) (raw)

Submission of the first full scale prototype chip for upgraded ATLAS pixel detector at LHC, FE-I4A

Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 2011

A new ATLAS pixel chip FE-I4 is being developed for use in upgraded LHC luminosity environments, including the near-term Insertable B-Layer (IBL) upgrade. FE-I4 is designed in a 130 nm CMOS technology, presenting advantages in terms of radiation tolerance and digital logic density compared to the 0.25 µm CMOS technology used for the current ATLAS pixel IC, FE-I3. The FE-I4 architecture is based on an array of 80×336 pixels, each 50×250 µm 2 , consisting of analog and digital sections. In the summer 2010, a first full scale prototype FE-I4A was submitted for an engineering run. This IC features the full scale pixel array as well as the complex periphery of the future full-size FE-I4. The FE-I4A contains also various extra test features which should prove very useful for the chip characterization, but deviate from the needs for standard operation of the final FE-I4 for IBL. In this paper, focus will be brought to the various features implemented in the FE-I4A submission, while also underlining the main differences between the FE-I4A IC and the final FE-I4 as envisioned for IBL.

Recent progress of the ATLAS Planar Pixel Sensor R&D Project

2011

The foreseen luminosity upgrade for the LHC (a factor of 5-10 more in peak luminosity by 2021) poses serious constraints on the technology for the ATLAS tracker in this High Luminosity era (HL-LHC). In fact, such luminosity increase leads to increased occupancy and radiation damage of the tracking detectors.

Planar Pixel Sensors for the ATLAS Upgrade: Beam Tests results

2012

The performance of planar silicon pixel sensors, in development for the ATLAS Insertable B-Layer and High Luminosity LHC (HL-LHC) upgrades, has been examined in a series of beam tests at the CERN SPS facilities since 2009. Salient results are reported on the key parameters, including the spatial resolution, the charge collection and the charge sharing between adjacent cells, for different bulk materials and sensor geometries. Measurements are presented for n + -in-n pixel sensors irradiated with a range of fluences and for ptype silicon sensors with various layouts from different vendors. All tested sensors were connected via bump-bonding to the ATLAS Pixel read-out chip.

A MCM-D-type module for the ATLAS pixel detector

IEEE Transactions on Nuclear Science, 1999

For the ATLAS experiment at the planned Large Hadron Collider LHC at CERN hybrid pixel detectors are being built as innermost layers of the inner tracking detector system. Modules are the basic building blocks of the ATLAS pixel detector. A module consists of a sensor tile with an active area of 16.4 mm x 60.4 mm, 16 read out IC's, each serving 24 x 160 pixel unit cells, a module controller chip, an optical transceiver and the local signal interconnection and power distribution busses. The dies are attached by flip-chip assembly to the sensor diodes and the local busses.

The ATLAS Inner Detector commissioning and calibration

The European Physical Journal C-Particles and Fields, 2010

The ATLAS Inner Detector is a composite tracking system consisting of silicon pixels, silicon strips and straw tubes in a 2 T magnetic field. Its installation was completed in August 2008 and the detector took part in data-taking with single LHC beams and cosmic rays. The initial detector operation, hardware commissioning and in-situ calibrations are described. Tracking performance has been measured with 7.6 million cosmic-ray events, collected using a tracking trigger and reconstructed with modular pattern-recognition and ...

Digital architecture and interface of the new ATLAS Pixel Front-End IC for upgraded LHC luminosity

2008

A new pixel Front-End Integrated Circuit is being developed in a 130 nm technology for use in the foreseen b-layer upgrade of the ATLAS pixel detector. Development of this chip is considered as an intermediate step towards super-LHC upgrade, and also allows having a smaller radius insertable pixel layer. The higher luminosity for which this chip is tuned implies a complete redefinition of the digital architecture logic with respect to the current ATLAS pixel Front-End. The new digital architecture logic is not based on a transfer of all pixel hits to the periphery of the chip, but on local pixel logic, local pixel data storage, and a new mechanism to drain triggered hits from the Double-Column. An overview of the new chip will be given with particular emphasis on the new digital logic architecture and possible variations. The new interface needed to configure and operate the chip will also be described.

A high-voltage pixel sensor for the ATLAS upgrade

Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 2018

High Voltage CMOS (HVCMOS) pixel sensors have been proposed for upgrade of the ATLAS experiment and for the tracking detectors at future colliders. They are implemented in commercial HVCMOS technologies, which makes the production cost effective when compared to hybrid pixel detectors. The HVCMOS detectors are monolithic, which means that the readout electronics and the sensor part are implemented on the same substrate. A high voltage is used to create a depletion region where the particle detection occurs. A large area prototype for the ATLAS experiment named ''ATLASpix'' has been designed and fabricated in the AMS 180 nm HVCMOS process technology. ATLASpix includes different design flavors in terms of pixel size and readout logic. HVCMOS pixel sensors have been fabricated using wafers of different resistivity. Design details and measurement results are presented.

Operation and performance of the ATLAS semiconductor tracker

2014

The semiconductor tracker is a silicon microstrip detector forming part of the inner tracking system of the ATLAS experiment at the LHC. The operation and performance of the semiconductor tracker during the first years of LHC running are described. More than 99% of the detector modules were operational during this period, with an average intrinsic hit efficiency of (99.74±0.04)%. The evolution of the noise occupancy is discussed, and measurements of the Lorentz angle, δ-ray production and energy loss presented. The alignment of the detector is found to be stable at the few-micron level over long periods of time. Radiation damage measurements, which include the evolution of detector leakage currents, are found to be consistent with predictions and are used in the verification of radiation background simulations.