Single-Stage Low-Power Quadrature RF Receiver Front-End: The LMV Cell (original) (raw)

A Single-Stage Low-Power Double-Balanced Mixer Merged with LNA and VCO

International Journal of Electrical and Computer Engineering (IJECE), 2017

This paper proposes three types of single stage low-power RF front-end, called double-balanced LMVs, by merging LNA, mixer, and voltage-controlled oscillator (VCO) exploiting a series LC (SLC) network. The low intermediate frequency (IF) or baseband signal can be directly sensed at the drain nodes of the VCO switching transistors by adding a simple resistor-capacitor (RC) low-pass filter (LPF). By adopting a double-balanced mixer topology, the strong leakage of the local oscillator (LO) at the IF output is effectively suppressed. Using a 65 nm CMOS technology, the proposed double-balanced LMVs (DB-LMVs) are designed. Oscillating at around 2.4 GHz ISM band, the phase noise of the proposed three DB-LMVs is −111 dBc/Hz at 1 MHz offset frequency. The simulated voltage conversion gain is larger than 36 dB and the double-side band (DSB) noise figure (NF) is less than 7.7 dB. The DB-LMVs consume only 0.2 mW dc power from 1-V supply voltage.

A 0.8V, 152 μW, 433 MHz Mixer-First Receiver with a Self-Adjusted Frequency Tracking Loop

IEEE Access, 2021

This paper presents a 433 MHz low-power receiver utilizing an N-path filter technique and a self-frequency tracking mechanism. Without the front-end amplifier, the mixer-first architecture can reduce power consumption significantly. A self-adjusted frequency tracking loop (SA-FTL) adjusts local oscillator (LO) frequency to approach input RF frequency automatically, thereby enhancing conversion gain and lowering return loss. The receiver, implemented in a <inline-formula> <tex-math notation="LaTeX">$0.18~\mu \text{m}$ </tex-math></inline-formula> CMOS process, achieves a sensitivity of −80 dBm at a bit error rate (BER) of 10<sup>−3</sup> and a data rate of 10 kb/s, while consuming <inline-formula> <tex-math notation="LaTeX">$152~\mu \text{W}$ </tex-math></inline-formula> from a 0.8V voltage supply.

IJERT-Low power Design and Analysis of Low Noise Amplifiers for RF receiver front end using 90nm CMOS

International Journal of Engineering Research and Technology (IJERT), 2013

https://www.ijert.org/low-power-design-and-analysis-of-low-noise-amplifiers-for-rf-receiver-front-end-using-90nm-cmos https://www.ijert.org/research/low-power-design-and-analysis-of-low-noise-amplifiers-for-rf-receiver-front-end-using-90nm-cmos-IJERTV2IS100924.pdf This letter presents the design of low-noise amplifiers for wireless receiver front ends. Several low noise amplifier topologies are implemented namely: (1) cascaded common-source amplifier, (2) folded cascode amplifier, (3) shunt feedback amplifier and (4) Current-Reuse g m boosted CG LNA. The amplifiers were implemented in a standard 90-nm CMOS process and were operated with a 1-V supply voltage. Low-noise amplifier measurements were taken for parameters such as power gain, noise figure, input matching, output matching, reverse isolation, stability, and linearity. Based on the employed figure-of-merit, the cascoded commonsource low-noise amplifier achieved the best performance among the four with a simulated gain of 13.8 dB and noise figure of 1.7 dB, which makes it comparable to previously available works.