Behavioral synthesis of analog systems using two-layered design space exploration (original) (raw)

A VHDL-AMS compiler and architecture generator for behavioral synthesis of analog systems

Proceedings of the conference on Design, automation and test in Europe - DATE '99, 1999

This paper presents a complete method for automatically translating VHDL-AMS behavioral-specifications of analog systems into op amp level net-lists of library components. We discuss the three fundamental aspects, that pertain to any behavioral synthesis environment: the specification language, the rules for compiling language constructs into a technology-independent, intermediate representation, and the synthesis (mapping) of representations to net-lists (topologies) of library components, so that performance constraints are satisfied. We motivate the effectiveness of the method by presenting our synthesis results for 5 examples.

AMGIE-A synthesis environment for CMOS analog integrated circuits

IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 2001

A synthesis environment for analog integrated circuits is presented that is able to drastically increase design and layout productivity for analog blocks. The system covers the complete design flow from specification over topology selection and optimal circuit sizing down to automatic layout generation and performance characterization. It follows a hierarchical refinement strategy for more complex cells and is process independent. The sizing is based on an improved equation-based optimization approach, where the circuit behavior is characterized by declarative models that are then converted in a sequential design plan. Supporting tools have been developed to reduce the total effort to set up a new circuit topology in the system's database. The performance-driven layout generation tool guarantees layouts that satisfy all performance constraints. Redesign support is included in the design flow management to perform backtracking in case of design problems. The experimental results illustrate the productiveness and efficiency of the environment for the synthesis and process tuning of frequently used analog cells.

A Decomposition-Based Symbolic Analysis Method for Analog Synthesis from Behavioral Specifications

VLSI: Systems on a Chip, 2000

This paper discusscs a technique for symbolic analysis of largc analog systems. The method exploits the hierarchical structure and uniformity of a system for producing compact symbolie expressions. The technique is based on decomposing a system through the method of tcaring [5] as opposed to traditional symbolic methods that llse nodal analysis. After producing the symbolic model ora system, a set ofredLlction rules is applied to the model. RedLlctions attempt 10 dccrease the number of arithmetic operations perronned for numetically evaluating the symbolic model. The discLlssed technique is useful for synthesis, inside an exploration-Ioop, as it avoids repeatedly computing the symbolic models.

Supporting analog synthesis by abstracting circuit behavior using a modeling methodology

For analog and mixed-signal circuit design a modeling methodology is needed which is well suited to the requirements of a structured synthesis flow. It ensures that the intended specification is met without over-design. Behavioral models are able to provide circuit level knowledge on higher abstraction levels by including non-idealities and parasitics from the circuit realization, which allows realistic comparison of different architectures. At the same time these models are fast enough to explore design space and optimize specification translation with respect to system performance measures. This paper shows how numerical, analytical, and symbolic methods as part of an integrated modeling methodology are used for model generation, model parameterization, and model refinement in order to improve and accelerate analog circuit synthesis

AN OPTIMIZATION-BASED TOOL FOR CIRCUIT LEVEL SYNTHESIS ANALOG INTEGRATED CIRCUITS

The goal of this paper is to present a tool for automatic sizing of analog basic integrated blocks using heuristics of non-linear optimization and an external electrical simulator. The methodology is based on the minimization of a cost function and constraint parameters related to circuit electrical characteristics. The methodology was implemented in Matlab using two heuristics of non-linear optimization, Simulated Annealing (SA) and Genetic Algorithms (GA). As electrical simulations we used the Smash simulator and the ACM MOSFET model. As design example, this paper shows the application of this methodology for the design of an active load differential amplifier using AMS 0.35µm technology.

Automatic Synthesis of Analog Integrated Circuits Including Efficient Yield Optimization

Computational Intelligence in Analog and Mixed-Signal (AMS) and Radio-Frequency (RF) Circuit Design, 2015

The goal of this paper is to present a tool for automatic synthesis of analog basic integrated blocks using the genetic algorithm heuristic and external electrical simulator. The methodology is based on the minimization of a cost function and a set of constraints in order to size circuit individual transistors. The synthesis methodology was implemented in Matlab and used GAOT (Genetic Algorithm Optimization Toolbox) as heuristic. For transistors simulation we used the Smash simulator and ACM MOSFET model, which includes a reduced set of parameters and is continuous in all regions of operation, providing an efficient search in the design space. As circuit design example, this paper shows the application of this methodology for the design of an active load differential amplifier in AMS 0.35um technology.

Exploration-based high-level synthesis of linear analog systems operating at low/medium frequencies

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2003

This paper presents a methodology for high-level synthesis of continuous-time linear analog systems. Synthesis results are architectures of op-amps, sized resistors and capacitors such that their ac behavior and total silicon area are optimized. Bounds for op-amp dc gain, unity-gain frequency, input, and output impedances are found as a byproduct of synthesis. Subsequently, a circuit synthesis tool can be used to synthesize the op-amps of an architecture. The paper details the architecture generation technique. Architecture generation produces alternative architectures for a system specification using the tabu search heuristic. Its main advantages over traditional methods is that it is application independent, does not require a library of block connection patterns, and is simple to implement. The paper also discusses the hierarchical, two-step parameter optimization that guides architecture generation. Experiments showed that linear analog systems operating at low/medium frequencies (like telecommunication systems and filters) can be synthesized in a reasonably long time and with reduced effort.

An evolutionary approach to automatic synthesis of high-performance analog integrated circuits

IEEE Transactions on Evolutionary Computation, 2003

This paper presents an analog integrated circuit synthesis system based on an evolutionary approach. The system contains several novel features. One of these is the high-performance optimization algorithm, which is a combination of evolutionary strategies and simulated annealing. Modeling of dc parameters is done via a fast dc simulator developed for this purpose whereas modeling of ac parameters can be done either with user-defined equations or with neural-fuzzy performance models trained from SPICE simulations. Another novel feature of the system is the incorporation of matching properties of devices. This way, the optimized circuit becomes tolerant to process variations. The synthesis system has been tested on several independent examples and synthesized circuits have been verified functionally with SPICE simulations. Finally, a prototype chip composed of the three examples has been manufactured. The measurement results have demonstrated the validity of the synthesis system on silicon.

Enhancing an Automatic Analog IC Design Flow by Using a Technology-Independent Module Generator

Performance Optimization Techniques in Analog, Mixed-Signal, and Radio-Frequency Circuit Design

This chapter presents a new methodology to enhance the optimization process of an analog integrated circuit synthesis tool, AIDA-C, by taking into account the floorplan of the circuit. The addition of the new Analog Module Generator (AMG) in the AIDA framework creates the possibility to efficiently explore the circuit floorplan during the optimization process and to improve the quality of the final floorplan by adding complex device structures enhancing the layout matching, symmetry, and routing, reducing some of the non-idealities to which analog integrated circuits are so sensitive. The performance enhancement attained with AMG is demonstrated using a well-known benchmark circuit, optimized by AIDA-C with and without taking into account AMG's complex structures in the evaluation of the circuit's floorplan.

Model based hierarchical optimization strategies for analog design automation

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014, 2014

The design of complex analog circuits by using flat optimization-based approaches is inefficient, even impossible, due to the high number of design variables and the growth of the cost of performance evaluation with the circuit size. Over the past two decades, top-down hierarchical design approaches have been developed and applied. They are based on hierarchical circuit decomposition and specification transmission from top-level to lower level blocks. However, such specification transmission is usually performed with little knowledge on the feasibility of the specifications, leading, therefore, to costly redesign iterations. Even if the specification transmission is successful, there is no guarantee that it is optimal in terms of e.g., power consumption or area occupation. To palliate this problem, two novel model-based hierarchical synthesis methods are proposed in this paper: Model-Based Hierarchical Optimization (MBHO) and Improved Model-Based Hierarchical Optimization (IMBHO). They are based on the concurrent design at higher and lower hierarchical levels and appropriate communication between the different processes. Experimental results on a filter example comparing the new approaches and the conventional top-down design approach are provided.