Low Power-Area GDI & PTL Techniques Based Full Adder Designs (original) (raw)
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AREA AND POWER EFFICIENT CMOS ADDER DESIGN BY HYBRIDIZING PTL AND GDI TECHNIQUE
In CMOS integrated circuit design there is a trade-off between static power consumption and technology scaling factors. Leakage power accounts for an increasingly larger portion of total power consumption in deep submicron technologies. Recently, in technology the power density has increased due to combination of higher clock speed, smaller process geometries and scaling factors, layout structure and greater functional integration.
Low Power 1-Bit Full Adder Circuit Using Modified Gate Diffusion Input ( GDI )
2016
Low Power techniques are becoming important and useful as the number of transistors is increasing every day. It is crucial to reduce the power dissipation for long life, more reliable and high performance systems. Gate Diffusion Input (GDI) is one technique to achieve low power. GDI requires less number of transistors as compared to corresponding CMOS logic. The basic GDI cell consists of only two transistors, where all the three terminals Gate, Source and Drain of the transistors are treated as inputs. GDI technique also has the advantage of less delay and reduced area. But the disadvantage of GDI is the output does not have a full swing of logic 1 and logic 0. In this paper basic GDI cell is modified to get a full swing for logic 1 and 0. This modified GDI cell is used to implement the full adder. Comparison results of basic GDI, Modified GDI, CMOS circuits are shown. These results are obtained from CADENCE VIRTUOSO based on 45nm technology with the supply voltage of 1.2V. Keyword...
Design of GDI Based Low Power and High-Speed CMOS Full Adder Circuits
2014
Power consumption and delay are two important considerations for VLSI systems. The objective of this project is to reduce the power and to reduce the delay which increases the speed. Adders are very important components in many applications such as microprocessor and digital signal processing (DSP) architectures. Full Adder is one of the core elements. It used in many of the complex arithmetic logic circuits like multiplication, division, addition. In this paper Full Adder has been generated by the Gate Diffusion Input (GDI) technique. The proposed full adder is simulated with Tanner EDA using 0.18μm CMOS Technology. By reducing the Transistor size, the power and delay are reduced. Simulation results show great improvement in terms of Power-Delay-Product (PDP).
LOW-POWER 1-BIT FULL-ADDER CELL USING ENHANCED PASS TRANSISTOR LOGIC AND POWER GATING
Adders have become one of the important components in the digital world, such that there exists no design without it. Adders are not only used for additions, but it is also one of the basic building blocks that have been used for many other functions such as subtractions, multiplications, and divisions etc. In the field of Very Large Scale Integration (VLSI), Adders are used as the basic component from processors to ASICs. Propagation delay, Power and Area are the acceptable Quality metrics of the designed products. Recent days has proved that the use of Complementary Pass Transistor Logic (CPL) and sleep transistor provides a drastic reduction in the power compared to CMOS logic. Power Gating is one such well known technique where a sleep transistor is added between actual ground rail and circuit ground. The device is turned off during sleep mode to cut-off the leakage path. This technique results in a substantial reduction in leakage at a minimal impact on performance. This paper has spread the focus on Low power Adder design based on PTLs, with reduced sub threshold leakage power consumption and ground bounce noise during sleep to active mode transition, thereby achieving 2.5% reduction in power without affecting other quality metrics of the design. The CPL design has been modeled and analyzed using TANNER EDA with TSMC MOSIS 250nm technology. In the present paper we will propose low leakage 1 bit CMOS full adder circuit in 90nm technology with supply voltage of 1V. Keywords: CPL, Power, VLSI, Adder
Study on various GDI Techniques for Low Power , High Speed Full Adder Design
2016
This paper is an outcome of a survey on different full adders design methodologies using gate diffusion input technique. Gate diffusion input is a technique of low power digital combination design. This technique as compared to other currently used logic design styles, allows less power consumption and reduced propagation delay for low power design of combinational digital circuits with minimum number of transistor. A comparison is also made on the basis of power, delay and area to find out the best possible design technique. This paper presents a detail performance of GDI Based 1-bit Full Adder Circuit for Low Power Applications. Different techniques like GDI, PTL-GDI and GDI-MUX for the designing of full adder is reviewed.
Design of a Full Adder using PTL and GDI Technique
In this paper an area and power efficient 9T adder design has been presented by hybridizing PTL and GDI techniques. The proposed adder design consists of 5 NMOS and 4 PMOS transistors. A PTL based 5T XOR-XNOR module has been proposed to improve area at 130nm technology. The proposed Hybrid full adder design is based on this area efficient 5T XOR-XNOR module design. Different logic functions can be implemented by only two transistors by using Gate diffusion input (GDI) approach. To improve area and power efficiency a cascade implementation of XOR module has been avoided in the proposed full adder. XOR-XNOR modules outputs act as input to Carry and Sum module which has been implemented by the GDI MUX. GDI approach is suitable for design of high speed, power efficient circuits with improved logic level swing and static power characteristics using a reduced number of transistors as compared to CMOS techniques. Simulations have been performed using tanner tool and Result shows that the proposed adder has an improvement of 62% in power over Existing Parallel Self-timed Adder (PASTA).
This paper proposes the design of a low power, high speed, energy efficient full adder using modified Gate Diffusion Input (GDI) and Mixed Threshold Voltage (MVT) scheme in 45nm technology. The proposed design on comparison with the traditional full adder composed of CMOS transistors, transmission gates and Complementary Pass-Transistor Logic (CPL), respectively, exhibited a considerable amount of reduction in terms of average power consumption (Pavg), peak power consumption (Ppeak), delay time, power delay product (PDP), energy delay product (EDP) as well as transistor count and hence surface area. Pavg is as low as 7.61×10−7 watt while Ppeak is as low as 6.21×10−5 watt, delay time is found to be 2.05nano second while PDP is computed to be as low as 1.56×10−15 Joule and EDP is evaluated to be as low as 3.20×10−24 Js for 0.9 volt power supply. The simulation of the proposed design has been performed in HSPICE and the layout has been designed in Microwind.
Design of low power full adder using MGDI logic
2020
Full adder is an essential component to design different digital systems and it is used in wide applications like microprocessor and microcontroller and also digital signal processors. There is a high command in electronic devices and circuits, and then it requires low power and high speed. Here, the present paper illustrates the significance of power, delay and a transistor count. The investigation and outline of 8TMGDI full adder style is observed. This full adder is maintaining some low power complexity. The presentation and application of the modified gate diffusion full adder are compared to other full adders like CMOS and GDI. The simulation results of the 8T modified gate diffusion full adder shown better power and delay values, when compared to the other full adders. This paper gives the best results in the low power technology. In 45nm Technology virtuoso tool, the proposed full adder is designed and compared.
Implementation of Low Power CMOS Full Adders Using Pass Transistor Logic
The efficiency of a system mainly depends on the performance of internal components present in the system. The internal components should be designed in such a way that they consume low power with high speed. Lot of components is in circuits including full-adder. This is mainly used in processors. A new Pass transistor full adder circuit is implemented in this paper. The main idea is to introduce the design of high performance and based pass transistor full adders which acquires less area and transistor count. The high performance of pass transistor low power full adder circuit is designed and the simulation has been carried out on Tanner EDA Tool. The result shows that the proposed full adder is an efficient full adder cell with least MOS transistor count that reduces the high power consumption and increases the speed. In this paper CMOS full adder circuits are designed to reduce the power and area and to increase the speed of operation in arithmetic application. To operate at ultra-low supply voltage, the pass logic circuit that cogenerates the intermediate XOR and XNOR outputs has been improved to overcome the switching delay problem
AREA AND POWER EFFICIENT CMOS ADDER DESIGN BY HYBRIDIZING PTL AND TECHNIQUE
In CMOS integrated circuit design there is a trade-off between static power consumption and technology scaling factors. Leakage power accounts for an increasingly larger portion of total power consumption in deep submicron technologies. Recently, in technology the power density has increased due to combination of higher clock speed, smaller process geometries and scaling factors, layout structure and greater functional integration. As results static power consumption is becoming more dominant state. This is a challenge for the CMOS integrated circuit designers. However the integrated CMOS designers do have a few methods which they can use to reduce this static power consumption. Since, these methods have some drawbacks. To attain lowest static power consumption one has to sacrifice design area and circuit performance. In this paper we proposed a new method to reduce static power in the CMOS VLSI circuit using dual stack approach without being penalized in area requirement and circuit performance.