State assignment for area minimization of sequential circuits based on cuckoo search optimization (original) (raw)
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State assignment for area minimization of sequential circuits based on cuckoo search optimization q
A major optimization problem in the synthesis of sequential circuits is State Assignment or State Encoding in Finite State Machines (FSMs). The state assignment of an FSM determines the complexity of its combinational circuit and thus area, delay, testability and power dissipation. Since optimal state assignment is an NP-hard problem and existing deter-ministic algorithms produce solutions far from best known solutions, we resort to the use of non-deterministic iterative optimization heuristics. This paper proposes the use of cuckoo search optimization (CSO) algorithm for solving the state assignment problem (SAP) of FSMs with the aim of minimizing area of the resulting sequential circuit. Results obtained from the CSO algorithm are compared with those obtained from binary particle swarm optimization (BPSO) algorithm, genetic algorithm (GA), and the well-known deter-ministic methods of NOVA and JEDI. The results indicate that CSO outperforms deter-ministic methods as well as other non-deterministic heuristic optimization methods.
Applied Soft Computing, 2013
State assignment (SA) for finite state machines (FSMs) is one of the main optimization problems in the synthesis of sequential circuits. It determines the complexity of its combinational circuit and thus area, delay, testability and power dissipation of its implementation. Particle swarm optimization (PSO) is a nondeterministic heuristic that optimizes a problem by iteratively trying to improve a candidate solution with regard to a given measure of quality. PSO optimizes a problem by having a population of candidate solutions called particles, and moving them around in the search-space according to a simple mathematical formulae. In this paper, we propose an improved binary particle swarm optimization (BPSO) algorithm and demonstrate its effectiveness in solving the state assignment problem in sequential circuit synthesis targeting area optimization. It will be an evident that the proposed BPSO algorithm overcomes the drawbacks of the original BPSO algorithm. Experimental results demonstrate the effectiveness of the proposed BPSO algorithm in comparison to other BPSO variants reported in the literature and in comparison to Genetic Algorithm (GA), Simulated Evolution (SimE) and deterministic algorithms like Jedi and Nova.
State assignment (SA) for finite state machines (FSMs) is one of the crucial synthesis steps in the design and optimisation of sequential circuits. In this study, we propose a majority-based evolution (MBE) SA algorithm that can be considered a variant of the well known differential evolution algorithm. Each individual is evolved based on selecting three random individuals, one of which is selected to be the best individual with a 50% probability. Then, for each state in the individual a selection is made with a 50% probability between keeping the current state or replacing it with a newly computed state. The bit values of the new state are determined based on the majority values of the state of the three selected individuals under a randomly generated probability within a predetermined range. The proposed algorithm is used for FSM state encoding targeting the optimisation of both area and power. Experimental results demonstrate the effectiveness of the proposed MBE SA algorithm in comparison with other evolutionary algorithms including genetic algorithm, binary particle swarm optimisation, Tabu search and simulated evolution.
A probabilistic pairwise swap search state assignment algorithm for sequential circuit optimization
State assignment (SA) for Finite State Machines (FSMs) has a significant impact on the area and power of synthesized sequential circuits. Due to the complexity of the state assignment problem and the limitations of existing deterministic solutions, evolutionary algorithms are employed for solving the state assignment problem. In this paper, we propose a probabilistic pairwise swap search (PPSS) state assignment algorithm. The algorithm is based on assigning probabilities for each pair of code swaps and intelligently updating those probabilities such that potentially useful code swaps will get high code swap probabilities and their chance of being explored is increased. Due to the fixed number of code swaps to be explored in each iteration, the algorithm explores code swaps in a gradual manner such that code swaps with high probability are explored before those with lower probability. The algorithm employs the use of Tabu lists to diversify search exploration and performs hill climbing when the solution does not improve by accepting the code swap that results in the next best solution from the current solution. The proposed algorithm is employed for FSM state encoding targeting the optimization of area and power. Experimental results demonstrate the effectiveness of the proposed PPSS state assignment algorithm in comparison to other evolutionary state assignment algorithms. Significantly better area and power results are achieved in comparison to all compared techniques.
A CAD Tool for the Optimal State Assignment of Sequential Synchronous Circuits
Assigning proper binary codes to the states of sequential circuits is a long studied problem known as state assignment. The choice of the numbers assigned to the states determines the final hardware structure and implementation requirements of the circuits. Conventional state assignment techniques can not be applied when arbitrary optimality criteria are defined. The problem can actually be seen as a search problem with a huge non-linear space. The nature of the space makes it impossible to find optimal solutions by conducting exhaustive, random or conventional search techniques. In this paper, a CAD tool is introduced which solves the problem for sequential synchronous circuits by means of a Genetic Algorithm (GA). The main advantage of the tool is the ability to cope with large circuits and optimize with respect to different objective functions. Moreover, it is free, easy-to-use and cross-platform.
Use of Particle Swarm Optimization to Design Combinational Logic Circuits
2003
This paper presents a proposal based on binary particle swarm optimization to design combinational logic circuits at the gatelevel. The proposed algorithm is validated using several examples from the literature, and is compared against a genetic algorithm (with integer representation), and against human designers who used traditional circuit design aids (e.g., Karnaugh Maps). Results indicate that particle swarm optimization may be a viable alternative to design combinational circuits at the gate-level.
Evolutionary Algorithms and Theirs Use in the Design of Sequential Logic Circuits
Genetic Programming and Evolvable Machines, 2000
In this paper an approach based on an evolutionary algorithm to design synchronous sequential logic circuits with minimum number of logic gates is suggested. The proposed method consists of four main stages. The first stage is concerned with the use of genetic algorithms (GA) for the state assignment problem to compute optimal binary codes for each symbolic state and construct the state transition table of finite state machine (FSM). The second stage defines the subcircuits required to achieve the desired functionality. The third stage evaluates the subcircuits using extrinsic Evolvable Hardware (EHW). During the fourth stage, the final circuit is assembled. The obtained results compare favourably against those produced by manual methods and other methods based on heuristic techniques.
Designing Genetic Algorithms for the State Assignment Problem
IEEE Transactions on Systems, Man and Cybernetics, 1995
Finding the best state assignment for implementing a synchronous sequential circuit is important for reducing silicon area or chip count in many digital designs. This State Assignment Problem (SAP) belongs to a broader class of combinatorial optimization problems than the well studied traveling salesman problem, which can be formulated as a special case of SAP. The search for a good solution is considerably involved for the SAP due to a large number of equivalent solutions, and no effective heuristic has been found so far to cater to all types of circuits.
Circuit Synthesis Using Particle Swarm Optimization
2006 IEEE International Conference on Computational Cybernetics, 2006
Particle Swarm Optimization (PSO) is a population-based search algorithm that is initialized with a population of random solutions, called particles. In a PSO scheme each particle flies through the search space with a velocity that is adjusted dynamically according with its historical behavior. Therefore, the particles have a tendency to fly towards the best search area along the search process. PSO is also an evolutionary computation technique well adapted to the automatic design of electronic devices. In this line of thought, this paper proposes a PSO based algorithm for logic circuit synthesis. The results show the statistical characteristics of this algorithm with respect to number of generations required to achieve the solutions. The results are compared with other two Evolutionary Algorithms (EAs), namely Genetic and Memetic Algorithms (GA and MA). I 1-4244-
On the Use of a Population-Based Particle Swarm Optimizer to Design Combinational Logic Circuits
2004
This paper extends our original proposal to use Particle Swarm Optimization (PSO) to design combinational logic circuits in which a binary representation was adopted. In this case, we study the impact of the representation adopted. For that sake, we adopt 2 integer representations (one of which is proposed by us) and we compare them with respect to our previous binary representation and with respect to a multiobjective genetic algorithm that uses an integer encoding. For our comparative study, we adopted several combinational logic circuits of one and several outputs whose designs have been previously studied in the specialized literature. Our results indicate that PSO can be a competitive algorithm for circuit design when using one of the integer representations proposed.