Design and Analysis of Low Power CMOS Charge Pump Circuits For Phase-Locked Loop (original) (raw)

DESIGN, IMPLEMENTATION AND COMPARISON OF VARIOUS CMOS CHARGE PUMPS

A charge pump is a kind of DC to DC converter that uses capacitors as energy storage elements to create a higher or lower voltage power source. Charge pumps make use of switching devices for controlling the connection of voltage to the capacitor. The use of charge transfer switches (CTSs) can improve the voltage pumping gain. Applying dynamic control to the CTSs can reduce reverse currents. This paper includes voltage and power analysis of various charge pump circuits. And a comparison is drawn between the three charge pumps analyzed.

High Performance CMOS Charge Pumps for Phase-locked Loop

Transactions on Electrical and Electronic Materials, 2015

Phase-locked-loops (PLL) have been employed in high-speed data transmission systems like wireless transceivers, disk read/write channels and high-speed interfaces. The majority of the researchers use a charge pump (CP) to obtain high performance from PLLs. This paper presents a review of various CMOS CP schemes that have been implemented for PLLs and the relationship between the CP parameters with PLL performance. The CP architecture is evaluated by its current matching, charge sharing, voltage output range, linearity and power consumption characteristics. This review shows that the CP has significant impact on the quality performance of CP PLLs.

A CMOS charge pump for low voltage operation

2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353), 2000

This paper proposes a low-voltage, high performance charge pump circuit suitable for implementation in standard CMOS technologies. The proposed charge pump utilises the cross-connected NMOS, voltage doubler, as a pumping stage. For low-voltage operation, where the performance of the NMOS is limited due to body effect, PMOS are used to increase the pumping gain. Simulations at 50 MHz have shown that for power supply voltages of 2V, 1.5V, 1.2V and 0.9V an output voltage of I1.5V, 8.4V, 6.5V and 4V can be generated respectively, using five pumping stages.

A Novel Charge Pump with Low Current for Low-Power Delay-Locked Loops

Circuits, Systems, and Signal Processing, 2017

In this paper, a new charge pump circuit for reducing charge and discharge currents with low power consumption is proposed. Using 1.8 V supply voltage, this proposed charge pump generates maximum 19.9 μA current. This charge pump is designed and simulated in TSMC 0.18 μm CMOS technology in order to be used in a delay-locked loop. One of the benefits of this circuit is its capability to be applied in a wide frequency range from 50 to 800 MHz with power consumption range of 410-740 μW. The proposed charge pump exploits feedback loop in order to achieve suitable current matching and also has a good characteristics in high frequencies.

Design Topologies of a CMOS Charge Pump Circuit for Low Power Applications

Electronics

Applications such as non-volatile memories (NVM), radio frequency identification (RFID), high voltage generators, switched capacitor circuits, operational amplifiers, voltage regulators, and DC–DC converters employ charge pump (CP) circuits as they can generate a higher output voltage from the very low supply voltage. Besides, continuous power supply reduction, low implementation cost, and high efficiency can be managed using CP circuits in low-power applications in the complementary metal-oxide-semiconductor (CMOS) process. This study aims to figure out the most widely used CP design topologies for embedded systems on the chip (SoC). Design methods have evolved from diode-connected structures to dynamic clock voltage scaling charge pumps have been discussed in this research. Based on the different architecture, operating principles and optimization techniques with their advantages and disadvantages have compared with the final output. Researchers mainly focused on designing the cha...

Charge Pump, Loop Filter and VCO for Phase Lock Loop Using 0.18µm CMOS Technology

This paper presents a Low power charge pump, second order low pass filter and voltage controlled oscillator for low power phase lock loop. The paper contains the detailed circuit diagram of charge pump, loop filter and voltage control oscillator with 1.8v power supply. The design has been realized using 0.18um CMOS technology. Here current starved voltage control oscillator is use for phase lock loop.

SEMICONDUCTOR INTEGRATED CIRCUITS: A novel CMOS charge-pump circuit with current mode control 110 mA at 2.7 V for telecommunication systems

Journal of Semiconductors, 2010

This paper presents a novel organization of switch capacitor charge pump circuits based on voltage doubler structures. Each voltage doubler takes a DC input and outputs a doubled DC voltage. By cascading voltage doublers the output voltage increases up to 2 times. A two-phase voltage doubler and a multiphase voltage doubler structures are discussed and design considerations are presented. A simulator working in the Q-V realm was used for simplified circuit level simulation. In order to evaluate the power delivered by a charge pump, a resistive load is attached to the output of the charge pump and an equivalent capacitance is evaluated. To avoid the short circuit during switching, a clock pair generator is used to achieve multi-phase non-overlapping clock pairs. This paper also identifies optimum loading conditions for different configurations of the charge pumps. The proposed charge-pump circuit is designed and simulated by SPICE with TSMC 0.35-m CMOS technology and operates with a 2.7 to 3.6 V supply voltage. It has an area of 0.4 mm 2 ; it was designed with a frequency regulation of 1 MHz and internal current mode to reduce power consumption.

Charge Pump Circuits for Low-voltage Applications

VLSI Design, 2002

In this paper, a low-voltage, high performance charge pump circuit, suitable for implementation in standard CMOS technologies is proposed. Its pumping operation is based on cascading several crossconnected NMOS voltage doubler stages. For very low-voltage applications (1.2 V, 0.9 V), where the performance of the NMOS transistors is limited due to body effect, two improved versions of the charge pump with cascaded voltage doublers (charge pump with CVD) are also proposed. The first utilises PMOS transistors (charge pump with CVD-PMOS) in parallel to the cross-connected NMOS transistors, while the second improves the pumping gain by boosting the clock amplitude (charge pump with CVD-BCLK). Simulations at 50 MHz have shown that a five-stages charge pump with CVD can achieve a 1.5-8.4 V voltage conversion. For the same stage number and frequency, an output voltage of 4 and 7.3 V can be generated from 0.9 V, by using the charge pump with CVD-PMOS and the charge pump with CVD-BCLK, respectively.

Power efficient charge pump in deep submicron standard cmos technology

IEEE Journal of Solid-State Circuits, 2003

A power efficient charge pump is proposed. The use of low voltage transistors and of a simple 2-phase clocking scheme allows the use of higher frequencies compared to conventional solutions, thus obtaining high current, high efficiency and small area. Measurements show good results for frequencies around 100MHz.

Novel CMOS Bulk-driven Charge Pump for Ultra Low Input Voltage

Radioengineering, 2016

In this paper, a novel bulk-driven cross-coupled charge pump designed in standard 90 nm CMOS technology is presented. The proposed charge pump is based on a dynamic threshold voltage inverter and is suitable for integrated ultra-low voltage converters. Due to a latchup risk, bulkdriven charge pumps can safely be used only in low-voltage applications. For the input voltage below 200 mV and output current of 1 µA, the proposed bulk-driven topology can achieve about 10 % higher efficiency than the conventional gate-driven cross-coupled charge pump. Therefore, it can be effectively used in DC-DC converters, which are the basic building blocks of on-chip energy harvesting systems with ultra-low supply voltage.