Sequence compaction for power estimation: theory and practice (original) (raw)

Hierarchical sequence compaction for power estimation

1997

This paper presents an effective technique for compacting a large sequence of input vectors into a much smaller one such that when the two sequences are applied to any circuit, the resulting power dissipations are nearly the same. Specifically, this paper introduces the hierarchical modeling of Markov chains as a flexible framework for capturing not only complex spatiotemporal correlations, but also dynamic changes in the characteristics of the input sequence. The new framework has a high degree of adaptability, i.e. the hierarchical model is dynamically grown according to the sequence behavior. Experimental results demonstrate that large compaction ratios can be obtained without a significant loss in accuracy (less than 5% on average) of power estimates.

Analytical model for high level power modeling of combinational and sequential circuits

Proceedings IEEE Alessandro Volta Memorial Workshop on Low-Power Design, 1999

In this paper, we propose a modeling approach that captures the dependence of the power dissipation of a (combinational or sequential) logic circuit on its input/output signal switching statistics. The resulting power macromodel, consists of a quadratic or cubic equation in four variables, that can be used to estimate the power consumed in the circuit for any given input/output signal statistics. Given a low-level (typically gate-level) description of the circuit, we describe a characterization process that uses a recursive least squares (RLS) algorithm by which such a equation-based model can be automatically built. The four variables of our model are the average input signal probability, average input switching activity, average input spatial correlation coefficient and average output zero-delay switching activity. This approach has been implemented and models have been built and tested for many combinational and sequential benchmark circuits. by the Semiconductor Research Corporation (SRC 97-DJ-484), with technical mentorship from Texas Instruments Inc.

Estimation of power dissipation using a novel power macromodeling technique

2000

Abstract In this paper, we develop a novel technique based on Markov chains to accurately estimate power sensitivities to primary inputs in CMOS sequential circuits. A key application of power sensitivities is to construct a complicated power surface in the specification-space so as to easily obtain the power dissipation under any distribution of primary inputs, thereby offering an effective power macromodel for high-level power estimation.

Power modeling for high-level power estimation

Very Large Scale Integration (VLSI) …, 2000

In this paper, we propose a modeling approach that captures the dependence of the power dissipation of a combinational logic circuit on its input/output signal switching statistics. The resulting power macromodel, consisting of a single four-dimensional table, can be used to estimate the power consumed in the circuit for any given input/output signal statistics. Given a low-level (typically gate-level) description of the circuit, we describe a characterization process by which such a table model can be automatically built. The four dimensions of our table-based model are the average input signal probability, average input transition density, average spatial correlation coefficient and average output zero-delay transition density. This approach has been implemented and models have been built for many benchmark circuits. Over a wide range of input signal statistics, we show that this model gives very good accuracy, with an RMS error of about 4% and average error of about 6%. Except for one out of about 10,000 cases, the largest error observed was under 20%. If one ignores the glitching activity, then the RMS error becomes under 1%, the average error becomes under 5% and the largest error observed in all cases is under 18%.

A Novel Approach for High-Level Power Modeling of Sequential Circuits Using Recurrent Neural Networks

2005 IEEE International Symposium on Circuits and Systems

In this work, we propose a novel power model for CMOS sequential circuits by using recurrent neural networks (RNN) to learn the relationship between input/output signal statistics and the corresponding power dissipation. The complexity of our neural power model has almost no relationship with circuit size and the numbers of inputs, outputs and flip-flops such that this power model can be kept very small even for complex circuits. Using such a simple structure, the neural power models can still have high accuracy because they can automatically consider the nonlinear characteristic of power distributions and the temporal correlation of the input sequences. The experimental results have shown that the estimations are still accurate with smaller variation even for short sequences. It implies that our power model can be used in various applications.

Power Macromodeling For High Level Power Estimation

Proceedings of the 34th Design Automation Conference, 1997

A modeling approach is presented that captures the dependence of the power dissipation of a combinational logic circuit on its input/output signal switching activity. The resulting power macromodel, consisting of a single three dimensional table, can be used to estimate the power consumed in the circuit for any given input/output signal statistics. Given a low-level (typically gatelevel) description of the circuit, we describe a characterization process by which such a table model can be automatically built. In contrast to other proposed techniques, this can be done for any given logic circuit without any user intervention, and applies to all possible input/output signal statistics; it does not require one to construct specialized analytical equations for the power dissipation. The three dimensions of our table-based model are the average input signal probability, average input transition density, and average output zero-delay transition density. This approach has been implemented and models have been built for many benchmark circuits. Over a wide range of input signal statistics, we show that this model gives very good accuracy, with an RMS error of under about 6%.

Estimation of power sensitivity in sequential circuits with power macromodeling application

1998

Abstract We propose a novel technique based on Markov chains to accurately estimate power sensitivities to primary inputs in CMOS sequential circuits. The power sensitivity defines the change in average power dissipation due to changes in the input signal specification. Such sensitivities are estimated as by-products of the average power estimation, leading to an efficient implementation.

Monte-Carlo approach for power estimation in sequential circuits

Proceedings European Design and Test Conference. ED & TC 97, 1997

In this paper we present a Monte-Carlo based statistical techniques for estimating power in sequential circuits. Mutually independent samples of power are generated by simulating multiple copies of the circuit. Since the approach is simulation-based, spatiotemporal correlations are automatically accounted for. The algorithm iterates until the user-speci ed a c curacy is achieved. Experimental results on ISCAS89 circuits show that reliable results can be obtained i n c onsiderably less time than that required by exhaustive simulation.

Analytical models for RTL power estimation of combinational and sequential circuits

… -Aided Design of Integrated Circuits and …, 2000

In this paper, we propose a modeling technique that captures the dependence of the power dissipation of a (combinational or sequential) logic circuit on its input/output signal switching statistics. The resulting power macromodel consists of a quadratic or cubic equation in four variables, that can be used to estimate the power consumed in the circuit for any given input/output signal statistics. Given a low-level (typically gate-level) description of the circuit, we describe a characterization process that uses a recursive least squares (RLS) algorithm by which such an equation-based model can be automatically built. This approach has been implemented and models have been built and tested for many combinational and sequential benchmark circuits.

Power Estimation in Sequential Circuitsy

… , 1995. DAC'95. 32nd Conference on, 1995

{ A new method for power estimation in sequential circuits is presented that is based on a statistical estimation technique. By applying randomly generated input sequences to the circuit, statistics on the latch outputs are collected, by simulation, that allow ecient p o w er estimation for the whole design. An important advantage of this approach is that the desired accuracy can be specied up-front b y the user; the algorithm iterates until the specied accuracy is achieved. This has been implemented and tested on a number of sequential circuits and found to be much faster than existing techniques. We can complete the analysis of a circuit with 1,452 ip-ops and 19,253 gates in about 4.6 hours (the largest test case reported previously has 223 ip-ops).