Ultimate Scaling of High-k Gate Dielectrics: Current Status and Challenges (original) (raw)
Related papers
Scaling the MOSFET gate dielectric: From high-k to higher-k? (Invited Paper)
Microelectronic Engineering, 2009
We discuss options for metal-oxide-semiconductor field-effect transistor (MOSFET) gate stack scaling with thin titanium nitride metal gate electrodes and high-permittivity ('high-k') gate dielectrics, aimed at gate-first integration schemes. Both options are based on further increasing permittivity of the dielectric stack. First, we show that hafnium-based stacks such as TiN/HfO 2 can be scaled to capacitance equivalent thickness in inversion (T inv ) of 10 Å and equivalent oxide thickness (EOT) of 6 Å by using silicon nitride instead of silicon oxide as a high-k/channel interfacial layer. This is based on the higher dielectric constant of Si 3 N 4 and on its resistance to oxidation. Although the nitrogen introduces positive fixed charges, carrier mobility is not degraded. Secondly, we investigate whether Ti-based 'higher-k' dielectrics have the potential to ultimately replace Hf. We discuss oxygen loss from TiO 2 as a main challenge, and identify two migration pathways for such oxygen atoms: In addition to well-known down-diffusion and channel Si oxidation, we have newly observed oxygen up-diffusion through the TiN metal gate, forming SiO 2 at the poly-Si contact. We further address the performance of Si 3 N 4 and HfO 2 as oxygen barrier layers.
IEEE Electron Device Letters, 2006
HfO 2 and HfSiON gate dielectrics with high-field electron mobility greater than 90% of the SiO 2 universal mobility and equivalent oxide thickness (EOT) approaching 1 nm are successfully achieved by co-optimizing the metal gate/high-k/bottom interface stack. Besides the thickness of the high-dielectrics, the thickness of the ALD TiN metal gate and the formation of the bottom interface also play an important role in scaling EOT and achieving high electron mobility. A phase transformation is observed for aggressively scaled HfO 2 and HfSiON, which may be responsible for the high mobility and low charge trapping of the optimized HfO 2 gate stack.
2006
HfO 2 and HfSiON gate dielectrics with high-field electron mobility greater than 90% of the SiO 2 universal mobility and equivalent oxide thickness (EOT) approaching 1 nm are successfully achieved by co-optimizing the metal gate/high-k/bottom interface stack. Besides the thickness of the high-dielectrics, the thickness of the ALD TiN metal gate and the formation of the bottom interface also play an important role in scaling EOT and achieving high electron mobility. A phase transformation is observed for aggressively scaled HfO 2 and HfSiON, which may be responsible for the high mobility and low charge trapping of the optimized HfO 2 gate stack.
Dual layer SrTiO3/HfO2 gate dielectric for aggressively scaled band-edge nMOS devices
Microelectronic Engineering, 2007
We have fabricated TiN/Poly-Si gated MOS devices with SrTiO 3 /HfO 2 dual layer gate dielectric. These gate dielectrics show EOT (Equivalent Oxide Thickness) scaling of less than 0.7 nm as well as large V fb shift in the nMOS direction after conventional gate first process. A sweet spot is observed for 0.5 nm SrTiO 3 where a band-edge effective work-function is obtained with improved EOT, reduced gate leakage and minimal hysteresis increase. But Sr diffuse into the interfacial layer leads to interface degradation. It is shown that proper PDA (post-deposition anneal) can improve interface quality while maintaining thinner EOT.
Highly manufacturable advanced gate-stack technology for sub-45-nm self-aligned gate-first CMOSFETs
IEEE Transactions on Electron Devices, 2000
Issues surrounding the integration of Hf-based high-κ dielectrics with metal gates in a conventional CMOS flow are discussed. The careful choice of a gate-stack process as well as optimization of other CMOS process steps enable robust metal/high-κ CMOSFETs with wide process latitude. HfO 2 of a 2-nm physical thickness shows a very minimal transient charge trapping resulting from kinetically suppressed crystallization. Thickness of metal electrode is also a critical factor to optimize physical-stress effects and minimize dopant diffusion. A hightemperature anneal after source/drain implantation in a conventional CMOSFET process is found to reduce the interface state density and improve the electron mobility. Even though MOSFET process using single midgap metal gate addresses fundamental issues related to implementing metal/high-κ stack, integrating two different metals on the same wafer (i.e., dual metal gate) poses several additional challenges, such as metal gate separation between n-and pMOS and gate-stack dry etch. We demonstrate that a dual metal gate CMOSFET yields high-performance devices even with a conventional gate-first approach if an appropriate metal separation between band-edge metal for nMOS and pMOS is incorporated. Optimization of dry-etch process enables gentle and complete removal of two different metal gate stacks on ultrathin high-κ layer.
Equivalent oxide thickness ͑EOT͒ scaling still remains one of the main facilitators to increase transistor performance. The use of rare-earth ͑RE͒ elements has been shown to effectively increase permittivity of the gate-stack interfacial layer between substrate and high-k dielectric, reducing its EOT contribution. In this paper, we have studied the optimal RE-to-SiO 2 ratio using Dy 2 O 3 as a test case. Capacitance-voltage and leakage current-voltage measurements were performed on Pt-gated capacitors with a SiO 2 /Dy 2 O 3 /Sc-doped HfO 2 gate stack and varying ratios of Dy 2 O 3 to SiO 2 after a 1000°C anneal. Optimal EOT-leakage performance was found for a Dy 2 O 3 -to-SiO 2 ratio of ϳ0.5 to 0.6.
IEEE Electron Device Letters, 2000
In this letter, ultrathin gadolinium oxide (Gd 2 O 3 ) high-k gate dielectrics with complementary-metal-oxidesemiconductor (CMOS)-compatible fully silicided nickel-silicide metal gate electrodes are reported for the first time. MOS capacitors with a Gd 2 O 3 thickness of 3.1 nm yield a capacitance equivalent oxide thickness of CET = 0.86 nm. The extracted dielectric constant is k = 13−14. Leakage currents and equivalent oxide thicknesses of this novel gate stack meet the International Technology Roadmap for Semiconductors targets for the near term schedule and beyond.
Influence of interlayer properties on the characteristics of high-k gate stacks
Solid-State Electronics
The significance of interface sharpness between interlayers and high-k oxides for the properties of transistor gate-stacks has been investigated. Energy band variation in the oxide is calculated by using literature data for the HfO 2 /SiO 2 interface, assuming two different cases for the interface plane: flat with a gradual depth variation of k-value and rough with an abrupt change of k. We demonstrate that the capacitive properties are similar, whereas tunneling properties considerably differ between the two cases. Furthermore, depth distributions of tunneling effective mass and dielectric constant have a substantial influence on the probability for charge carrier tunneling through the oxide stack and for the determination of capacitance equivalent oxide thickness (CET).