Reliability degradation with electrical, thermal and thermal gradient stress in interconnects (original) (raw)
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A reliability model for electromigration-induced failure in metal interconnects under time-dependent stress is introduced. In contrast to existing reliability models that are based upon the assumption that stress is constant throughout the useful life of a system, this model includes provisions for the more realistic situation where both thermal stress and current stress are time-dependent. A single parameter which can be represented as a real number is used to incorporate the total effects of the stress history making this approach applicable for dynamic power/thermal management algorithms.
2006
Thermal effects are becoming a limiting factor in high performance circuit design due to the strong temperature dependence of leakage power, circuit performance, IC package cost and reliability. While many interconnect reliabil- ity models assume a constant temperature, this paper analyzes the effects of temporal and spatial thermal gradients on interconnect lifetime in terms of electromigration. For temporal thermal variations, we present a physics-based dynamic model for estimating interconnect lifetime for any time-varying temperature/current profile, and this model returns reliability equivalent temperature and current density that can be used in traditional reliability analysis tools. For spatial temperature gradients, we give close bounds in terms of uniformly distributed temperatures to estimate the lifetime of interconnects subject to non-uniform temperature distribution. Our results are verified with numerical simulations and reveal that blindly using the maximum temperatur...
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A hierarchical scheme with cells and modules is crucial for managing design complexity during a large integrated circuit design. We present a methodology for thermal aware cell-based electromigration analysis suitable for integrating electromigration reliability analysis into a conventional IC design flow. A block or cell is characterized for reliability while it is characterized for power and timing. Reusing cell characterization data significantly reduces computational load while analyzing a full-chip layout. During full-chip analysis, we compute a layout-level temperature profile from cell power dissipations using a Fast Fourier Transform based algorithm. The described full-chip reliability assessment methodology has been implemented in an interconnect reliability CAD tool. We have exercised the tool to demonstrate performance-reliability tradeoff and the significance of thermalaware reliability analysis for true reliability aware design.
Microelectronics Journal, 2003
A panel was organized at the Therminic 2002 workshop to address the question posed in the title of this summary paper. Brief presentations were made by the six panelists, followed by an open discussion among Workshop participants. The focus of the panel was on reliability, not performance, and on systems, not parts. While the panel recognized the availability of various specialized analytical tools at a handful of leading research institutions and with expert individuals, it was felt that the industry at large is still transitioning from the use of simple thermal design rules to a more detailed physics based methodology. The current state-of-the-art of thermal metrology was outlined. An overview of the temperature-reliability relationships at the component and system levels was provided. Some of the emerging thermal challenges associated with the evolution of three-dimensional on-chip interconnect architectures were identified. The role of uncertainty analysis in predictions was emphasized. A primary conclusion was to focus on the prediction of thermally influenced risks in current and future products, based on a sound physics based approach.
Interconnect lifetime prediction under dynamic stress for reliability-aware design
IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004., 2004
Thermal effects are becoming a limiting factor in highperformance circuit design due to the strong temperaturedependence of leakage power, circuit performance, IC package cost and reliability. While many interconnect reliability models assume a constant temperature, this paper presents a physics-based model for estimating interconnect lifetime for any time-varying temperature/current profile. This model is verified with numerical solutions. With this model, we show that designers may be more aggressive with the temperature profiles that are allowed on a chip. In fact, our model reveals that when the temperature magnitude variation is small, average temperature (instead of worst-case temperature) can be used to accurately predict interconnect lifetime, allowing for significant design margin reclamation in reliability-aware design. Even when the variation of temperature magnitude is large, our model shows that using the maximum temperature is still too conservative for interconnect lifetime prediction. Therefore, our model not only increases the accuracy of reliability estimates, but also enables designers to consider more aggressive designs. This model is similarly useful for temperature-aware dynamic runtime management.
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Integration, 2018
The power elements are the weak parts of integrated circuits (ICs), in fact, through these elements the power is usually dissipated as heat with unavoidable thermal and mechanical stress. On the contrary the logic parts of ICs stay at lower temperatures. This gives rise to two effects: the non-uniform generation of the heat across the die and the temperature gradients. Understanding these phenomena is very important to choose the right location of sensitive components, like thermal sensors, in order to improve reliability. As a consequence, the knowledge of the temporal evolution of the temperature distribution plays a very important role to improve both design and lifetime. Here we show how a single IR sensor based experimental setup is suitable to catch very fast thermal events performing high spatial resolution. We demonstrate the effectiveness of the method maps for three IC samples where an accurate thermal modeling for reliability has been obtained and validated, greatly improving the overall quality.
Microelectronics Journal, 2007
We have developed a set of methodologies for thermal aware circuit-level reliability analysis with either Al or Cu metallization in a circuit layout and implemented it in a public domain reliability CAD tool, SysRel. SysRel utilizes a hierarchical reliability analysis flow, with interconnect trees treated as the fundamental reliability unit, that sufficiently captures the differences in electromigration failure between Al and Cu metallizations. Under similar test conditions, the electromigration reliability of Al and Cu interconnect trees demonstrates significant differences because of the differences in interconnect architectural schemes. Using the best estimates of material parameters and an analytical model, we present a detail comparison of electromigration reliability of a sample test-structure as well as of actual circuit layouts with Al and Cu dual-damascene interconnect systems. We also demonstrate fast thermal-analysis in SysRel for circuit performance driven chip-level reliability assessment. r
Interconnect thermal modeling for accurate simulation of circuit timing and reliability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2000
We apply three-dimensional finite element analysis to study the thermal coupling between nearby interconnects. We find that the temperature rise in current-carrying lines is significantly influenced by a dense array of lines in a nearby metal level. In contrast, thermal coupling between just two neighboring parallel lines is insignificant for most geometries. Design rules for average root-mean-square current density are provided for specific geometries given the requirement that the interconnect temperature be no more than 5 C above the substrate temperature. Semi-empirical formulae for coupling effects are presented based on the numerical results. A procedure is proposed to implement the formulae in computer-aided design tools.
Quality and Reliability Engineering International, 1994
A new method is presented to evaluate the resistance to electromigration of on-chip interconnects. The method is based on the high resolution in-situ electrical resistance technique. During high temperature and high current density stress measurements, two types of processes occur simultaneously: structure-relaxation and electromigration. In order to study these processes separately, the experimental conditions are adapted. The electrical resistance and TCR is measured before and after structure-relaxation and/or electromigration. Using Matthiessen's rule, it is possible to separate the contribution of the resistivity variation from the variation in geometry. The first process causes a decrease of the resistivity, whereas the second causes an increase. The influence of Cu-addition and deposition temperature is also investigated. Correlation of the resistivity variations with conventional mean time to failure (MTTF) data is demonstrated. As a consequence, with our short-time method, predictions of the resistance to electromigration of on-chip interconnects can be made after typical test times of 24 to 48 hours.