New optimal layer assignment for bus-oriented escape routing (original) (raw)

Escape routing for staggered-pin-array PCBs

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2011

To accommodate the ever-growing pin number of complex PCB designs, the staggered pin array is introduced for modern designs with higher pin density. However, the escape routing for staggered pin arrays, which is a key component of PCB routing, is significantly different from that for grid arrays. This paper presents a routing algorithm for the escape routing for staggered-pin-array PCBs. We first analyze the properties of staggered pin arrays, and propose an orthogonal-side wiring style that fully utilizes the routing resource of the staggered pin array. An LP/ILP based algorithm is presented to solve the staggeredpin-array escape routing problem. Experimental results show that our approach successfully completed the routing for all testcases efficiently and effectively.

Simultaneous Escape Routing using Network Flow Optimization

Malaysian Journal of Computer Science

With the advancement in technology, the size of electronic components and printed circuit boards (PCB) is becoming small while the pin count of each component is increasing. This has necessitated the use of ball grid array (BGA) type of components where pins are attached under the body of component as a grid. The problem of routing pins from under the body of component to the boundary of the component is known as escape routing. It is often desirable to perform ordered simultaneous escape routing (SER) to facilitate area routing and produce elegant PCB design. The task of SER is non-trivial, given the small size of components and hundreds of pins arranged in random order in each component that needs ordered connectivity. In this paper, first we propose flow models for different inter pin capacities. We then propose linear network flow optimization model that simultaneously solves the net ordering and net escape problem. The model routes maximum possible nets between two components of the PCB, by considering the design rules. Comparative analysis shows that the proposed optimization model performs better than the existing routing algorithms in terms of number of nets routed.

Mobility based Net Ordering for Simultaneous Escape Routing

International Journal of Advanced Computer Science and Applications

With the advancement in electronics technology, number of pins under the ball grid array (BGA) are increasing on reduced size components. In small size components, a challenging task is to solve the escape routing problem where BGA pins escape towards the component boundary. It is often desirable to perform ordered simultaneous escape routing (SER) to facilitate area routing and produce elegant Printed Circuit Board (PCB) design. Some heuristic techniques help in finding the PCB routing solution for SER but for larger problems these are time consuming and produce sub-optimal results. This work propose solution which divides the problem into two parts. First, a novel net ordering algorithm for SER using network theoretic approach and then linear optimization model for single component ordered escape routing has been proposed. The model routes maximum possible nets between two components of the PCB by considering the design rules based on the given net ordering. Comparative analysis shows that the proposed net ordering algorithm and optimization model performs better than the existing routing algorithms for SER in terms of number of nets routed. Also the running time using proposed algorithm reduces to O(2 N E/2) + O(2 N E/2) for ordered escape routing of both components. This time is much lesser than O(2 N E) due to exponential reduction.

An efficient pre-assignment routing algorithm for flip-chip designs

2009

The flip-chip package is introduced for modern IC designs with higher integration density and larger I/O counts. In this paper, we consider the pre-assignment flip-chip routing problem with predefined connections between driver pads and bump pads. This problem has been shown to be much more difficult than the free-assignment one, but is more popular in real-world designs because the connections between driver pads and bump pads are typically pre-determined by IC or packaging designers. Based on the concept of routing sequence exchange, we propose a very efficient global routing algorithm by computing the weighted longest common subsequence (WLCS) and the maximum planar subset of chords (MPSC) for pre-assignment flip-chips. We observe that the existing work over constrains the capacity of a routing tile, which might miss some critical solution space with a better routing solution (e.g., smaller wirelength), and provide a remedy for this insufficiency to identify a better solution in a more complete solution space. We also develop a constant-time routability analyzer to check if a given set of wires can pass through a tile. Experimental results show that our router can achieve a 122× speedup with even better solution quality (same routability with slightly smaller wire-length), compared with a state-of-the-art flip-chip router based on integer linear programming (ILP).

A new approach to routing of two-layer printed circuit board

International Journal of Circuit Theory and Applications, 1981

This paper presents a new method for routing two-layer printed circuit boards with fixed geometry, i.e. alternate columns of pins and vias. Circuit components are mounted on top of the board, and conductor wires are to be laid on the board such that circuit connections can be properly made. The proposed approach gives 100 per cent routability. The method consists of three steps, namely: partitioning of multi-pin nets into 2-pin subnets, via assignment, and routing on the tho layers. In comparison with the traditional unidirectional routing, the method offers more flexibility and it requires usually about half as many vias. A computer program based on the presented algorithms was written. Its implementation is presented along with testing examples.

Optimal routing algorithms for pin clusters in high-density multichip modules

ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005., 2005

As the circuit densities and transistor counts are increasing, the package routing problem is becoming more and more challenging. In this paper, we study an important routing problem encountered in typical high-end MCM designs: routing within dense pin clusters. Pin clusters are often formed by pins that belong to the same functional unit or the same data bus, and can become bottlenecks in terms of overall routability. Typically, these clusters have irregular shapes, which can be approximated with rectilinear convex boundaries. Since such boundaries have often irregular shapes, a traditional escape routing algorithm may give unroutable solutions. In this paper, we study how the positions of escape terminals on a convex boundary affect the overall routability. For this purpose, we propose a set of necessary and sufficient conditions to model routability outside a rectilinear convex boundary. Given an escape routing solution, we propose an optimal algorithm to select the maximal subset of nets that are routable outside the boundary. After that, we focus on an integrated approach to consider routability constraints (outside the boundary) during the actual escape routing algorithm. Here, we propose an optimal algorithm to find the best escape routing solution that satisfies all routability constraints. Our experiments demonstrate that we can reduce the number of layers by 17% on the average, by using this integrated methodology.

A Provably Good Global Routing Algorithm in Multilayer IC and MCM Layout Designs

Operations Research and Cyber-Infrastructure, 2009

Given a multilayer routing area, we consider the global routing problem of selecting a maximum set of nets, such that every net can be routed entirely in one of the given layers without violating the physical capacity constraints. This problem is motivated by applications in multilayer IC and multichip module (MCM) layout designs. The contribution of this paper is threefold. First, we formulate the problem as an integer linear program (ILP). Second, we modify an algorithm by Garg and Könemann for packing linear programs to obtain an approximation algorithm for the global routing problem. Our algorithm provides solutions guaranteed to be within a certain range of the global optimal solution, and runs in polynomial-time even if all, possibly exponentially many, Steiner trees are considered in the formulation. Finally, we demonstrate that the complexity of our algorithm can be significantly reduced in the case of identical routing layers.

An efficient approach to multilayer layer assignment with an application to via minimization

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1999

In this paper we present an efficient heuristic algorithm for the post-layout layer assignment and via minimization pr £ oblem of multilayer gridless integrated circuit (IC), printed cir ¤ cuit board (PCB), and multichip module (MCM) layouts. We formulate the multilayer layer assignment problem by introducing ¥ the notion of the extended conflict-continuation (ECC) graph. When ¦ the formulated ECC graph of a layer assignment problem is ¥ a tree, we show that the problem can be solved by an algorithm which § is both linear time and optimal. When the formulated ECC grapḧ is not a tree, we present an algorithm which constructs a © sequence of maximal induced subtrees from the ECC graph, then applies our linear time optimal algorithm to each of the induced ¥ subtrees to refine the layer assignment. Our experiments show that, on average, the number of vertices of an induced subtr ee found by our algorithm is between 12% and 34% of the total number of vertices of an ECC graph. This indicates that our algorithm is able to refine a large portion of the layout optimally on each refinement, thus, producing highly optimized layer assignment solutions. We applied this algorithm to the via minimization problem and obtained very encouraging results. We achieved © 13%-15% via reduction on the routing layout generated by the V4R router [1], which is a router known to have low usage of vias. Our algorithm has been successfully applied to routing examples of over 30 000 wire segments and over 40 000 vias. Finally, we outline how our layer assignment algorithm can also be used for delay and crosstalk minimization in high-performance IC, PCB, and MCM designs. I. INTRODUCTION A S very large scale integration (VLSI) technology advances, interconnection and packaging technologies have become bottlenecks in system performance. For advanced integrated circuit (IC) designs, four to six routing layers are ! commonly used in high-performance and high-density designs. " Multichip module (MCM) technology was developed to # increase packing densities, eliminate the packaging level of interconnections, and provide more layers for routing. In both the # multilayer IC and MCM designs, the designer or automatic layout $ tools may use variable widths and spacings to optimize performance. % This often results in multilayer gridless layouts. Because multilayer gridless routing is a complex threedimensional " general area routing problem, it

Algorithms and bounds for layer assignment of MCM routing

IEEE Transactions on Very Large Scale Integration Systems, 1994

In the power dissipation of the double and single edge triggered systems are shown. It can be seen that the single edge triggered system has a higher level of power dissipation. For example, at 33 Mbits/s the SET system has a power dissipation equal to the DET system operating at 40 Mbits/s. Furthermore, under idle conditions when no new data enters the system, the ratio of energy dissipated in DET to SET systems is 0.62. The actual energy dissipation in the SET system was about 130 pJ higher than in the DET system, which translates to a 17% greater energy dissipation in the SET system.

Placement and Routing in VLSI design Problem Using Single Row Routing Technique

2007

Two major problems are involved in VLSI design, namely, the placement of components and routing between these components. Single row routing problem is a combinatorial optimization problem of significant importance for the design of complex VLSI multi layer printed circuit boards (PCB's). The design involves conductor routing that makes all the necessary wiring and interconnections between the PCB modules, such as pins, vias, and backplanes. In very large systems, the number of interconnections may exceed tens of thousands. Therefore, we have to optimize the wire routing and interconnections and thus determine the efficient designs. Kernighan-Lin algorithm, traveling salesman problem, simulated annealing algorithm and single row routing problem are used to find the best design. Included here are some simple examples to find the results. A simulation program using Microsoft Visual C++ is developed to simulate the single row routing problem using the simulated annealing algorithm....