Electrical Runaway in AlGaN/GaN HEMTs: Physical Mechanisms and Impact on Reliability (original) (raw)
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Electrical overstress in AlGaN/GaN HEMTs: study of degradation processes
Solid-State Electronics, 2004
We study degradation mechanisms in 50 lm gate width/0.45 lm length AlGaN/GaN HEMTs after electrical overstresses. One hundred nanosecond long rectangular current pulses are applied on the drain contact keeping either both of the source and gate grounded or the source grounded and gate floating. Source-drain pulsed I-V characteristics show similar shape for both connections. After the HEMT undergoes the source-drain breakdown, a negative differential resistance region transits into a low voltage/high current region. Changes in the Schottky contact dc I-V characteristics and in the source and drain ohmic contacts are investigated as a function of the current stress level and are related to the HEMT dc performance. Catastrophic HEMT degradation was observed after I stress ¼ 1:65 A in case of the Ôgate floatingÕ connection due to ohmic contacts burnout. In case of the Ôgate groundedÕ connection, I stress ¼ 0:45 A was sufficient for the gate failure showing a high gate susceptibility to overstress. Backside transient interferometric mapping technique experiment reveals a current filament formation under both HEMT stress connections. Infrared camera observations lead to conclusion that the filament formation together with a consequent high-density electron flow is responsible for a dark spot formation and gradual ohmic contact degradation.
Investigation of High-Electric-Field Degradation Effects in AlGaN/GaN HEMTs
IEEE Transactions on Electron Devices, 2008
High-electric-field degradation phenomena are investigated in GaN-capped AlGaN/GaN HEMTs by comparing experimental data with numerical device simulations. Under power-and OFF-state conditions, 150-h DC stresses were carried out. Degradation effects characterizing both stress experiments were as follows: a drop in the dc drain current, the amplification of gate-lag effects, and a decrease in the reverse gate leakage current. Numerical simulations indicate that the simultaneous generation of surface (and/or barrier) and buffer traps can account for all of the aforementioned degradation modes. Experiments also showed that the power-state stress induced a drop in the transconductance at high gate-source voltages only, whereas the OFF-state stress led to a uniform transconductance drop over the entire gate-source-voltage range. This behavior can be reproduced by simulations provided that, under the power-state stress, traps are assumed to accumulate over a wide region extending laterally from the gate edge toward the drain contact, whereas, under the OFF-state stress, trap generation is supposed to take place in a narrower portion of the drain-access region close to the gate edge and to be accompanied by a significant degradation of the channel transport parameters.
AlGaN/GaN HEMT device reliability and degradation evolution: Importance of diffusion processes
Microelectronics Reliability, 2011
A methodology based on combined electrical trapping analysis with UV-assisted preparation of trap states and electroluminescence analysis was developed to gain detailed understanding of trap generation in AlGaN/GaN HEMTs during off and on-state stress. This is used to identify electronic trap location laterally and vertically in a device structure and the nature of the degradation mechanism. We identify the generation of traps with activation energies in the range from 0.45 to 0.65 eV near the gate edge on its drain side in AlGaN/GaN HEMTs as electronic traps in the AlGaN device layer, as a result of on-and off-state stress. Degradation studied on devices subjected to stress under different backplate temperatures, points to diffusion processes playing an important role for early device degradation. Diffusion constants showed thermal activation energies of $0.26 eV consistent with diffusion processes along dislocations, with possible additional contributions from bulk diffusion accelerated by converse/inverse piezo-electric strain and leakage currents.
Physics of electrical degradation in GaN high electron mobility transistors
2009
The deployment of GaN high electron mobility transistors (HEMT) in RF power applications is currently bottlenecked by their limited reliability. Obtaining the required reliability is a difficult issue due to the high voltage of operation. In order to improve reliability, it is essential to develop detailed physical understanding of the fundamental degradation mechanisms. In this thesis, we investigate the physical mechanisms behind the electrical degradation of GaN HEMTs by performing systematic stress experiments on devices provided by our industrial collaborators. These devices are electrically stressed under various bias conditions while regularly characterized by a benign characterization suite. We observe that electrical stress beyond a critical voltage results in an increase in drain resistance, a decrease in maximum drain current, and a sharp increase in reverse gate current. We show that this mode of degradation is driven by electric field and that current is less relevant. Behind this degradation is trap formation that occurs at the critical voltage. To understand this, we have developed a new trap-analysis methodology. It is found that under stress, the density of traps increases in the AlGaN barrier layer in the proximity to the gate edge on the drain side of the device. We show that this degradation is enhanced under mechanical uniaxial tensile strain that is externally applied to the device. From our experiments, we propose a degradation mechanism of defect formation through the inverse piezoelectric. In this mechanism, high vertical electric field at the gate edge under high voltage increases tensile stress in the AlGaN layer due to piezoelectricity of the material. When the elastic energy in the crystal exceeds a critical value, crystallographic defects are formed. These defects trap electrons and reduce drain current as well as provide leakage paths and increase gate current. We theoretically validate the plausibility of this hypothesis and provide a model for the critical voltage that agrees with experimental observations. Unlike conventional wisdom, hot electrons do not appear to be the direct cause of electrical degradation in the devices that we study. Our studies suggest several possibilities to improving the electrical reliability of GaN HEMTs.
A study on current collapse in AlGaN/GaN HEMTs induced by bias stress
IEEE Transactions on Electron Devices, 2003
Drain current collapse in AlGaN/GaN HEMTs has been studied systematically by applying bias stress to the device. The collapse was suppressed by light illumination with energy smaller than the bandgap. The position dependence of the light illumination and the measurement of series source and drain resistances revealed that the collapse was caused by the surface states between the gate and drain electrodes, which captured electrons injected from the gate. The current collapse was eliminated by the passivation of the device surface with Si 3 N 4 film.
Electrostatic Mechanisms Responsible for Device Degradation in AlGaN/GaN HEMTs
The World Academy of Research in Science and Engineering
The various factors that are responsible for device degradation are examined. The interplay between Non-Idealities in GaN HEMTs, traps, polarization, Origin of 2DEG, Current Collapse, Virtual gate, is analyzed and quantified. The various factors that helps in getting desired device characteristics regarding performance are studied and methods for achieving their satisfactory values are reviewed.
Reverse bias stressing in AlGaN/GaN high electron mobility transistors (HEMTs) compelled severe degradation of drain current (I DS) whereas gate current (I G) remained largely unaffected. Besides, the response of access region conductivity to pulse drives was found to deteriorate gradually as a result of stress, and an interacting deep level in the form of kink effect was observed. Post degradation, SEM imaging evidenced the field-induced formation of protruding particles, immediately adjacent to the gate electrode. Auger spectroscopy and elemental mapping chemically identified these insulating particles as gallium oxide. Barrier/channel consumption in the form of electrochemical oxidation is thus held responsible for I DS degradation whereas I G degradation is entirely attributed on the presence of passivation layer. SEM micrographs of the (a) tested, and (b) untested finger of a À80 V bias stressed HEMT. (c) Auger spectra from an insulating particle, whereas (d) and (e) are oxygen and gallium elemental maps of the entire frame (c).
Effects of gate shaping and consequent process changes on AlGaN/GaN HEMT reliability
physica status solidi (a), 2012
The effect of gate shape and its necessary fabrication process on the reliability of AlGaN/GaN high electron mobility transistors (HEMT) was studied on devices fabricated on the same wafer, using DC and pulsed HEMT analysis. Simulations were used to determine the difference in electric field on the surface and in the barrier for the three gate shapes studied, I-shaped, slanted and recessed slanted. Prior to each electrical characterization during stress, devices were exposed to ultraviolet illumination to probe only newly generated traps rather than the filling of pre-existing electronic traps. Degradation was seen to increase with electric field strength; in each device type traps were generated by device stress at the location of the peak electric field. It was found that HEMTs with I-shaped gates showed larger degradation under the same stress conditions than devices with slanted gates. This was due to a higher electric field at the interface between the SiN x passivation and the AlGaN barrier layer resulting in higher surface trap generation. HEMTs with slanted recessed gates showed indications of barrier trapping while surface trapping effects played a smaller role.
Comparison of reliability of 100 nm AlGaN/GaN HEMTs with T-gate and SAG-gate technology
Microelectronics Reliability, 2018
The effect of gate technology and semiconductor passivation on the switching speed and device reliability has been investigated. By reducing the parasitic capacitances and reducing the passivation induced surface charge density a median lifetime of around 10 6 h at a channel temperature of 125°C and a current-gain cutoff frequency of 74 GHz for a T-gate technology has been achieved. By electroluminescence and TEM cross-sectioning of a stressed device a local inhomogeneous pit formation process was found as the major degradation mechanism for the decrease of the saturation current.