A New General Topology for Cascaded Multilevel Inverters With Reduced Number of Components Based on Developed H-Bridge (original) (raw)
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A New General Topology for Cascaded Multilevel Inverters Based on Developed H Bridge
A new general cascaded multilevel inverter using developed H-bridges is proposed. The proposed topology requires a lesser number of dc voltage sources and power switches and consists of lower blocking voltage on switches, which results in decreased complexity and total cost of the inverter. These abilities obtained within comparing the proposed topology with the conventional topologies from aforementioned points of view. A new algorithm to determine the magnitude of dc voltage sources is proposed. The performance and functional accuracy of the proposed topology using the new algorithm in generating all voltage levels for a 31-level inverter are confirmed by simulation and experimental results.
Cascaded Multilevel Inverter Topology Based on Cascaded H-Bridge Multilevel Inverter
Energies
A three-phase multilevel inverter topology for use in various applications is proposed. The present topology introduces a combination of a cascaded H-bridge multilevel inverter with a cascaded three-phase voltage source inverter (three-phase triple voltage source inverter (TVSI)). This combination will increase the number of voltage levels generated when using fewer components compared with the conventional multilevel inverter topologies for the same voltage levels generated. The other advantage gained from the proposed configuration is the assurance of a continuous power supply to the grid in case of failure in one part of the proposed configuration. In addition, the voltage stresses on switches are reduced by half compared if each part in the proposed topology is working independently. The comparison of the proposed topology with some conventional multilevel inverter topologies is presented. The proposed topology is built in the SIMULINK environment and is simulated under various loads in addition to being connected to the grid. Phase-shifted pulse width modulation technique is used to generate the required switching pulses to drive the switches of the proposed topology. The inverter is experimentally implemented in the lab, and the switching pulses are generated with the help of MicroLabBox produced by dSPACE (digital signal processing and control engineering) company. The simulation and experimental results and their comparisons are presented to verify the proposed topology's effectiveness and reliability.
New Topology of Cascaded H-Bridge Multilevel Inverter
This paper mainly deals with three different topologies of cascaded H-Bridge multilevel inverter. The Existing Topology is a general type of multilevel inverter and has two DC sources for each phase. In Proposed Topology-I the number of DC sources has been reduced to one for all the three phases and the usage of transformers comes into picture. Proposed Topology-II has also only one DC source for all the three phases and the number of switches has been reduced than compare to all other proposed topologies of Cascaded H-bridge multilevel inverter. MATLAB simulations has been carried out for all three Topologies and compared with each other.
New Cascaded H-Bridge Multilevel Inverter Topology with Reduced Number of Switches and Sources
In this paper mainly focused on the design and implementation of new topology in a single phase five level cascaded H-bridge multilevel inverter by using only a five switches and two DC power source. The main objective of this paper is to increase number of levels with a low number of switches and sources at the output without adding any complexity to the power circuit. The main merit of the new topology is to reduce the lower total harmonic distortion, lower electromagnetic interference generation and high output voltage. In this paper, various carrier pulse width modulation techniques are proposed, which can minimize the total harmonic distortion and enhances the output voltages from proposed work of five level inverter. The various switching topologies of single-phase five level cascaded H-bridge multilevel inverters have been analyzed in this paper. It is justified that the new topology can be recommended to single phase five level Cascaded H-bridge inverter for better performance in comparison with conventional method. The simulation is done by Mat Lab 8.0 version software.
A Cascaded H-Bridge Multilevel Inverter with Reduced Number of Switches
Regular, 2020
This paper presents simulation of a 5-level cascaded H-bridge multilevel inverter, with reduce the number of power switching devices in the current flow direction. The propose topology consists of a five switches with double DC sources. The analysis is designing a new topology for a singlephase cascaded multilevel H-bridge inverter (CHBMLI), with a focus on the number of power switching devices in the current flow direction.Conduction and switching losses have to be reduced to achieve higher performance operation of power electronic devices.Multilevel inverters are designed to achieve the desired voltages of output from different DC sources.A analysis of the simulated power loss values is deals with based on how the power switch reduction led to the loss decreases.
An improved topology of cascaded multilevel inverter with low switch count
International Journal of Power Electronics, 2020
An improved topology of the multilevel inverter is described in this paper. Proposed topology is comprised of the basic module to get positive levels at the output. An H-bridge can be formed to obtain ac output. Developed topology significantly reduces the number of IGBTs, DC voltage sources, gate drivers for the same number of levels. Different algorithms are presented to determine the number of levels, switches, total blocking voltage and total standing voltage. Comparison of the proposed topology with the conventional cascaded multilevel inverters and other existing topologies in the literature has been carried out to show the advantages of the newly proposed topology. The operation and performance of the proposed multilevel inverter are verified by suitable experimental results with a single phase 15-level multilevel inverter considering resistive and inductive loads.
Comparison of Different Topologies of Cascaded H-Bridge Multilevel Inverter
This paper mainly deals with three different topologies of cascaded H-Bridge multilevel inverter. The Existing Topology is a general type of multilevel inverter and has two DC sources for each phase. In Proposed Topology-I the number of DC sources has been reduced to one for all the three phases and the usage of transformers comes into picture. Proposed Topology-II has also only one DC source for all the three phases and the number of switches has been reduced than compare to all other proposed topologies of Cascaded H-bridge multilevel inverter. MATLAB simulations has been carried out for all three Topologies and compared with each other.
Novel 5 Level Cascaded H-Bridge Multilevel Inverter Topology
International Journal of Engineering Trends and Technoloy, 2015
This paper represents Novel 5 level cascade H-bridge multilevel inverter using only 6 switches and two DC power source. The main aim of this paper is to increase number of levels with Reduced Number of Switches and Sources at the output without adding any complication to the power circuit. The main aim of the novel topology is to decrease the lower whole harmonic distortion and high output voltage. In this paper pulse width modulation technique is used to implement this topology which can minimize the total harmonic distortion and enhances the output voltages. The hardware of multilevel Inverter circuits has been done using Proteus-7.8 software. An AVR (ATmega16) microcontroller is used to generate pulses for controlling the multilevel inverter circuit and result are show in DSO (digital Storage Oscilloscope).
COMPARATIVE STUDY OF VARIOUS CASCADED H-BRIDGE MULTILEVEL INVERTER TOPOLOGIES
TJPRC, 2014
Multilevel inverters are becoming more popular in the power conversion systems for high power and power quality demanding applications. The MATLAB based simulation on simulink platform is presented for three various topologies of Single Phase cascaded H-bridge Multilevel Inverter for 5, 7 and 9 levels. A detailed comparison of various Topologies is presented in the paper based on number of power devices used, Total Harmonic Distortion, average voltage stress, maximum voltage stress and utilization factor. The Topology I and Topology II are cheap and efficient because number of conducting power devices are less as compared to the conventional Topology.
Journal of Operation and Automation in Power Engineering, 2014
In this paper, a new cascaded multilevel inverter by capability of increasing the number of output voltage levels with reduced number of power switches is proposed. The proposed topology consists of series connection of a number of proposed basic multilevel units. In order to generate all voltage levels at the output, five different algorithms are proposed to determine the magnitude of DC voltage sources. Reduction of the used power switches and the variety of DC voltage sources magnitudes are two main advantages of the proposed topology. These results are obtained by comparison of the proposed inverter with the H-bridge cascaded multilevel inverter and one of recently presented topologies. The remarkable ability of the proposed topology with its algorithms in generating all voltage levels (even and odd) is verified through PSCAD/EMTDC simulation and experimental results of a 17-level inverter.