An Optimal DPM Based Energy-Aware Task Scheduling for Performance Enhancement in Embedded MPSoC (original) (raw)
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Energy-Efficient Scheduling Based on Task Migration Policy Using DPM for Homogeneous MPSoCs
Increasing the life span and efficiency of Multiprocessor System on Chip (MPSoC) by reducing power and energy utilization has become a critical chip design challenge for multiprocessor systems. With the advancement of technology, the performance management of central processing unit (CPU) is changing. Power densities and thermal effects are quickly increasing in multi-core embedded technologies due to shrinking of chip size. When energy consumption reaches a threshold that creates a delay in complementary metal oxide semiconductor (CMOS) circuits and reduces the speed by 10%-15% because excessive on-chip temperature shortens the chip's life cycle. In this paper, we address the scheduling & energy utilization problem by introducing and evaluating an optimal energy-aware earliest deadline first scheduling (EA-EDF) based technique for multiprocessor environments with task migration that enhances the performance and efficiency in multiprocessor systemon-chip while lowering energy and power consumption. The selection of core and migration of tasks prevents the system from reaching its maximum energy utilization while effectively using the dynamic power management (DPM) policy. Increase in the execution of tasks the temperature and utilization factor (u i) on-chip increases that dissipate more power. The proposed approach migrates such tasks to the core that produces less heat and consumes less power by distributing the load on other cores to lower the temperature and optimizes the duration of idle and sleep times across multiple CPUs. The performance of the EA-EDF algorithm was evaluated by an extensive set of experiments, where excellent results were reported when compared to other current techniques, the efficacy of the proposed methodology reduces the power and energy consumption by 4.3%-4.7% on a utilization of 6%, 36% & 46% at 520 & 624 MHz operating frequency when particularly in comparison to other energy-aware methods for MPSoCs. Tasks are running and accurately scheduled to make an energy-efficient processor by controlling and managing the thermal effects on-chip and optimizing the energy consumption of MPSoCs.
Energy-Efficient Scheduling Based on Task Migration Policy Using DPM for燞omogeneous MPSoCs
Computers, Materials & Continua
Increasing the life span and efficiency of Multiprocessor System on Chip (MPSoC) by reducing power and energy utilization has become a critical chip design challenge for multiprocessor systems. With the advancement of technology, the performance management of central processing unit (CPU) is changing. Power densities and thermal effects are quickly increasing in multi-core embedded technologies due to shrinking of chip size. When energy consumption reaches a threshold that creates a delay in complementary metal oxide semiconductor (CMOS) circuits and reduces the speed by 10%-15% because excessive on-chip temperature shortens the chip's life cycle. In this paper, we address the scheduling & energy utilization problem by introducing and evaluating an optimal energy-aware earliest deadline first scheduling (EA-EDF) based technique for multiprocessor environments with task migration that enhances the performance and efficiency in multiprocessor systemon-chip while lowering energy and power consumption. The selection of core and migration of tasks prevents the system from reaching its maximum energy utilization while effectively using the dynamic power management (DPM) policy. Increase in the execution of tasks the temperature and utilization factor (u i) on-chip increases that dissipate more power. The proposed approach migrates such tasks to the core that produces less heat and consumes less power by distributing the load on other cores to lower the temperature and optimizes the duration of idle and sleep times across multiple CPUs. The performance of the EA-EDF algorithm was evaluated by an extensive set of experiments, where excellent results were reported when compared to other current techniques, the efficacy of the proposed methodology reduces the power and energy consumption by 4.3%-4.7% on a utilization of 6%, 36% & 46% at 520 & 624 MHz operating frequency when particularly in comparison to other energy-aware methods for MPSoCs. Tasks are running and accurately scheduled to make an energy-efficient processor by controlling and managing the thermal effects on-chip and optimizing the energy consumption of MPSoCs.
Power Gating Aware Task Scheduling in MPSoC
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000
Shrinking the feature size allows more and better functions on a single chip. However, it makes multiprocessor system-on-chip (MPSoC) more susceptible to various reliability threats. Power supply noise is a major reliability problem faced by low power MPSoCs using power gating techniques. Powering on and off a processing unit in MPSoCs will induce large power/ground (P/G) noise and can cause timing divergence and even functional errors in surrounding processing units. Previous work on resilient architectures mainly focused on power/thermal management and neglected the important side-effect: P/G noise induced by power gating. In this paper, for the first time, we formulate a task scheduling problem with the consideration of P/G noise based on our detailed P/G noise analysis platform for MPSoC. Two efficient algorithms are proposed to reduce noise protection penalty and improve MPSoC performance. Our experiments show that both simulated annealing and heuristic algorithms can achieve on average 25% performance improvement together with up to 80% noise protection penalty saving compared with the conservative stop-go method for short tasks (shorter than 20 K clock cycles). For longer tasks up to 200 K clock cycles, the performance improvement of our methods will become relatively low. However, we can still achieve at least 35.2% noise protection penalty saving. Furthermore, a lightweight online adjustment strategy accompanying the offline scheduling method is proposed to adapt to runtime variations and improve reliability.
Scheduling Based Energy Optimization Technique
international journal for research in applied science and engineering technology ijraset, 2020
At the operating system level, multi-core and multiprocessor system on chip started a new computing era but brought various twofold scheduling challenges in current developed thermal aware algorithms for multi-core processors. An offline thermal aware scheduling algorithm is proposed for improvement in multi core embedded system in case of energy, reliability and performance of a multi core system has been introduced. Due to shrinking of chip size power densities are increasing due to this increase in the temperature of chip occurs that reduces the processor’s speed in multi-core embedded system. Peak temperature on chip adversely affects the life span of chip. Task migration is a common way to avoid peak temperature values in multi core system. These tasks have been migrated in a multi core system which produces more heat to such individual core that has low temperature. The proposed method keeps tradeoff between keeping the workload balanced and task scheduling. In this research, a suitable scheduling mechanism assign tasks to the core that has less temperature by considering power and performance of the multi-core system. For attaining stability in temperature among multiple cores results are evaluated by comparing different task migration methods which are introduced previously. All types of hot and cold tasks are considered to predict temperature by using thermal history. The scheduling policy attains maximum efficiency in terms of energy by considering only those cores that are executing some tasks in highest energy state such as running state while considering all other cores in lowest energy state such as sleep or a deep sleep mode state.
Power-aware scheduling with effective task migration for real-time multicore embedded systems
Concurrency and Computation: Practice and Experience, 2012
A major design issue in embedded systems is reducing the power consumption since batteries have a limited energy budget. For this purpose, several techniques such as Dynamic Voltage and Frequency Scaling (DVFS) or task migration are being used. DVFS allows reducing power by selecting the optimal voltage supply, while task migration achieves this effect by balancing the workload among cores. This paper focuses on power-aware scheduling allowing task migration to reduce energy consumption in multicore embedded systems implementing DVFS capabilities. To address energy savings, the devised schedulers follow two main rules: migrations are allowed at specific points of time and only one task is allowed to migrate each time. Two algorithms have been proposed working under real-time constraints. The simpler algorithm, namely, Single Option Migration (SOM) only checks just one target core before performing a migration. In contrast, the Multiple Option Migration (MOM) searches the optimal target core. In general, the MOM algorithm achieves better energy savings than the SOM algorithm, although differences are wider for a reduced number of cores and frequency/voltage levels. Moreover, the MOM algorithm reduces energy consumption as much as 40% over the Worst Fit (WF) algorithm.
Energy Efficiency in Processors- A Survey
International journal of engineering research and technology, 2018
Energy being consumed in a circuit has been a major concern in the electronic industry and also in Digital System Design. Hence, to reduce the energy consumed by the underlying circuits, CMOS circuits were preferred. With the advancement in the integration technology, more transistors could be fit on the chip. This however led to increase in the energy dissipation. In a computer system, the processors memory and the Disk subsystems are the power hungry units. The numbers of computing systems are increasing drastically and will keep dissipating the energy and thus have an impact on environment too. This paper presents a review of various techniques in energy optimisation at all levels of the processor and hence suggests the ways to optimise the energy along the optimisation metrics associated with each of the technique. KeywordsEnergy, cache, hardware, Dynamic Power, Circuits,
Multi-level energy/power-aware design methodology for MPSoC
Journal of Parallel and Distributed Computing, 2017
h i g h l i g h t s • Multi-level design space exploration for Multiprocessor Systems-on-Chip (MPSoC). • Design exploration at the functional and transactional level. • Integration of runtime power optimization in the design flow. • A simulation time of less 1 s at the functional level and 160-190 s at the transactional level. • An average error of 1.59% of the transactional level results compared to physical implementations.
Scheduling for Better Energy Efficiency on Many-Core Chips
Many-core chips are especially attractive for data center operators providing cloud computing service models. With the advance of many-core chips in such environments energy-conscious scheduling of independent processes or operating systems (OSes) is gaining importance. An important research question is how the scheduler of such a system should assign the cores to the OSes in order to achieve a better energy utilization. In this paper, we demonstrate that many-core chips offer new opportunities for extremely lightweight migration of independent processes (or OSes) running bare-metal on the many-core chip. We then show how this intra-chip migration can be utilized to achieve a better performance per watt ratio by implementing a hierarchical power-management scheme on top of dynamic voltage and frequency scaling (DVFS). We have implemented and tested the proposed techniques on the Intel Single Chip Cloud Computer (SCC). Combining migration with DVFS we achieve, on average, a 25–35% better performance per watt over a DVFS-only solution.
Evaluating Energy-Aware Task Allocation Strategies for MPSOCS
2006
Because of current market trends, the evaluation of task allocation strategies in multiprocessor system-on-chips (MPSoCs) must take into account both performance and energy consumption. Furthermore, complex interconnection structures, such as networks-on-chip (NoCs), must be considered. Simulators for the evaluation of energy consumption of detailed communication patterns in NoCs are available, as well as performance simulators that consider detailed task execution in processors. However, in order to evaluate task allocation strategies in MPSoCs, these two types of simulation models must be combined, since communication and computation events interfere with each other. Besides that, this simulator must implement low-power mechanisms, such as dynamic voltage scaling (DVS), in order to evaluate allocation algorithms that explore the trade-off between performance and energy. A cycle-accurate simulation of the processor and communication behaviors, however, would be too time-consuming, making impossible a fast exploration of different allocation algorithms. This work presents an MPSoC simulator that implements the appropriate abstractions for a precise evaluation of the energy consumption of task allocation algorithms that explore DVS, which is based on the scheduling of synthetic task graphs. A NoC mesh topology is considered, due to its simplicity and scalability. Experiments that implement the allocation of task graphs using different bin-packing heuristics combined with DVS demonstrate the energy-performance design space that may be explored by task allocation algorithms.
Electrical Engineering (ICEE), 2011
Mapping and Scheduling are two central and critical steps in design flow of the Networks on Chips (NoCs). They deal with implementation of the applications on NoCs. In this paper a novel energy aware algorithm, called EAMS, for mapping and scheduling of concurrent applications to NoC platforms is developed. It is considered that, the NoC architecture consists of a set of heterogeneous IP cores. The introduced algorithm finds a mapping of the tasks of the application to available IP cores so that the overall energy consumption, meeting task deadlines, is minimized.