Efficient consistency checking of scenario-based product-line specifications (original) (raw)
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Requirements Engineering, 2013
Modern software-intensive systems typically consist of multiple components that provide many functions by their interaction. Moreover, often not only a single product, but a whole product line with different compositions of components and functions must be developed. To cope with this complexity, engineers need intuitive, but precise means for specifying the requirements for these systems and require tools for automatically finding inconsistencies within the requirements, because inconsistencies could lead to costly iterations in the later development. In recent work, we proposed a technique for the scenario-based specification of interactions in product lines by a combination of Modal Sequence Diagrams and Feature Diagrams. Furthermore, we elaborated an efficient consistency-checking technique based on a dedicated model-checking approach for product lines. In this paper, we report on further evaluations that underline significant performance benefits of our approach. We describe further optimizations and detail on how we encode the consistency-checking problem for a model-checker. Many modern software-intensive systems consist of multiple components interacting together to deliver the intended functionality. Often, these systems come in many variants (products) and are managed together as a software product line. This variability is the source of * FNRS research fellow
Logic Verification of Product-Line Variant Requirements
2012 African Conference for Sofware Engineering and Applied Computing, 2012
Formal verification of variant requirements has gained much interest in the software product line (SPL) community. Feature diagrams are widely used to model product line variants. However, there is a lack of precisely defined formal notation for representing and verifying such models. This paper presents an approach to modeling and verifying SPL variant feature diagrams using first-order logic. It provides a precise and rigorous formal interpretation of the feature diagrams. Logical expressions can be built by modeling variants and their dependencies by using propositional connectives. These expressions can then be validated by any suitable verification tool. A case study of a Computer Aided Dispatch (CAD) system variant feature model is presented to illustrate the verification process.
4 Logic Verification of Product-Line Variant Requirements
2016
Formal verification of variant requirements has gained much interest in the software product line (SPL) community. Feature diagrams are widely used to model product line variants. However, there is a lack of precisely defined formal notation for representing and verifying such models. This paper presents an approach to modeling and verifying SPL variant feature diagrams using first-order logic. It provides a precise and rigorous formal interpretation of the feature diagrams. Logical expressions can be built by modeling variants and their dependencies by using propositional connectives. These expressions can then be validated by any suitable verification tool. A case study of a Computer Aided Dispatch (CAD) system variant feature model is presented to illustrate the verification process.
Simulation-Based Abstractions for Software Product-Line Model Checking
fundp.ac.be
Software Product Line (SPL) engineering is a software engineering paradigm that exploits the commonality between similar software products to reduce life cycle costs and time-to-market. Many SPLs are critical and would benefit from efficient verification through model checking. Model checking SPLs is more difficult than for single systems, since the number of different products is potentially huge. In previous work, we introduced Featured Transition Systems (FTS), a formal, compact representation of SPL behaviour, and provided efficient algorithms to verify FTS. Yet, we still face the state explosion problem, like any model checking-based verification. Model abstraction is the most relevant answer to state explosion. In this paper, we define a novel simulation relation for FTS and provide an algorithm to compute it. We extend well-known simulation preservation properties to FTS and thus lay the theoretical foundations for abstraction-based model checking of SPLs. We evaluate our approach by comparing the cost of FTS-based simulation and abstraction with respect to productby-product methods. Our results show that FTS are a solid foundation for simulation-based model checking of SPL.
Symbolic model checking of software product lines
… Conference on Software …, 2011
We study the problem of model checking software product line (SPL) behaviours against temporal properties. This is more difficult than for single systems because an SPL with n features yields up to 2 n individual systems to verify. As each individual verification suffers from state explosion, it is crucial to propose efficient formalisms and heuristics.
Methods, techniques and tools for product line model verification
2008
Requirements for a product line have thus to be expressed in terms of features shared by all members of the product line, known as commonality, and distinct features of individual members, known as variability. Identifying and representing variability is an important aspect of product line devel opment. In order to be able to model and manage common and variable features, they have to be documented in a variability model. Feature diagram (FD) is a notation that is currently used to express variability models. Feature diagrams model the variability of features at a relatively high level of granularity. Their main purposes are (i) to capture feature commonalities and variabilities, (ii) to represent dependencies between features, and (iii) to determine combinations of features that are all owed and disallowed in the product line model (PLM). All the above can present multiple problems in the models of produ ct lines, problems that, from an industrial point of view, are highly expensive. Just like Pohl and other authors, we have not found in literature a method covering up the different criteria to be verified on a PLM. In the same way, we have found a lack of criteria unification with regard to the characteristics that must be verified, and a lack of language unification used in the rigid processes of verification found in literature. «To our knowledge, specialised techniques for software product line inspections, reviews, or walkthroughs have not be en proposed» [Polh et al. 05]. On the other hand, consistency checking of the requirement specification in domain engineering is still an open issue [Lauenroth, Pohl 07]. Motivated by these lacks, we suggest a PLM verification process focused in correctness evaluation on these types of models. We firstly do a bibliographic search that permit us make an inventor y of some techniques. We then go on to formalisation work of each criterion, particularly those for model verification, with propositional logic. Next, we have do integration work through MAP formalism, in order to propose a PLM correctness verification process that can be carried out in different ways. We have validated this approach through a real case study and implementation of the proposed MAP process model in a computational tool. Part II Research Presentation 2. Research problem, methodology and justification 26 2.1 Research problem 26 2.2 Research methodology 26 2.3 Justification 26 Part III State of the art on V&V in RE 3.1 Definition of Verification 30 3.2 Definition of Validation 30 3.3 Verification vs. Validation 31 3.4 Desirable characteristics to verify 34 3.5 Desirable characteristics to validate 40 3.6 Verification and validation techniques 45 3.7 Conclusion 48 Part IV Verification of Product Line Models 4.1 Methods proposed 50 4.2 Feature Meta-Model 63 4.3 {Characteristics to verify} + {techniques}* + {lessons}* 65 4.4 General lessons 79 4.5 Conclusion 82 Part V Multi-method of Verification 5 The Approach 84 5.1 Context and MAP formalism 84 5.2 MAP model of the approach 86 5.3 Context models of the MAP 87 5.4 Discussion 97 5.5 Conclusion 98
VAMOS 2009, 3rd International Workshop on Variability Modelling of Software-intensive Systems, 2009
The verification of variability models is recognized as one of the key challenges for automated development of product lines. Some computational tools have been proposed to verify product line models and product line configurations models. VMWare is a tool integrating different criteria to verify structural and semantic correctness of models derived from the FORE metamodel. Our tool gives the possibility of (i) build feature-based product line models and product line configuration models, (ii) verify their structural and semantic correctness in a completely automated manner and (iii) import/export them in XMI files.