Effective algorithms for cache-level compression (original) (raw)

Abstract

Compression at the cache level has the potential to increase microprocessor performance by decreasing the cache miss rate and increasing the e ective bandwidth by transmitting compressed data. This paper presents four compression algorithms that would be suitable for use in a compressed cache architecture and shows the results of using them to compress SPEC95 benchmarks. These algorithms exhibit a 7.8% to 99.8% improvement in compression ratio over an algorithm known to be e ective for cache compression.

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References (7)

1. REFERENCES
2. T. Bell, J. Cleary, and I. Witten. In Text Compression, Published b y P r entice Hall, 1 9 9 0 .
3. D. Burger and T. Austin. The SimpleScalar tool set, version 2.0. In Computer Architecture News, pages 13{25, 1997.
4. D. Citron and L. Rudolph. Creating a wider bus using caching techniques. In Proc. of the First IEEE Symposium on High-Performance Computer Architecture, pages 90{99, 1995.
5. F. Douglis. The compression cache: Using on-line compression to extend physical memory. In Proc. of the Winter USENIX Conference, pages 519{529, 1993.
6. D. Hu man. A method for the construction of minimum-redundancy codes. In Proc. of the I.R.E., pages 1098{1101, 1958.
7. M. Kjelso, M. Gooch, and S. Jones. Design and performance of a main memory hardware data