Approaches for Monitoring Vectors on Microprocessor Buses (original) (raw)
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where he chairs the Department of Information Engineering. He was a faculty member at the Illinois Institute of Technology when he authored this article. Liu's research interests include distributed processing and computer networks. Liu received the BSEE and Mfdegrees from the National Chiao Tung University in Taiwan and the PhD degree from the University of Illinois at Chicago. Ranjani Parthasarathi is a development engineer in the Business Communications Group of Indchem Electronics in India, where she participates in application-specific IC (ASIC) design for processing Indian languages. Parthasarathi received the BS degree from Madras University in India and the MS degree from the Illinois Institute of Technology, where she coauthored this article. She is a member of the IEEE.
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E3S Web of Conferences
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Accountability is an important issue when buses are to be use for transport purposes. This research is principally aimed at the design and implementation of a simple and effective digital bus passenger counter. The work is mainly the design and construction of an electronics counter, counts the number of passengers going into or out of a bus or the number of cars going into or out of a gate. The set of methods and principles used in achieving the circuit are called the top-down methodology. The actual state of the entrance which coincides with the exit was noted. Two-switch system was employed in order to avoid double counting, thus, counting is done in one direction. The switches are connected in such a way that a pulse is sent only when they are triggered in one direction, this results to the introduction of a transistor for its switching ability. The output of the transistor is connected to the display driver, which in turn is connected to the seven segment display. The circuit counts a maximum of 999 after which it resets to zero. The real implementation of the devise is done on this work.
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A new microsystem is presented which is able to process measurements including feature extraction and classification for local process monitoring. The heart of the microsystem is a 16-bit digital signal processor which can operate at up to 100 MIPS (million instructions per second). The extracted features are stored in a large non-volatile memory and are used for a long term trend analysis. Current and predicted faults are displayed locally and announced to the staff or a host computer via field bus or internet. The microsystem has been applied to an autonomous bearing fault diagnosis .
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Bit-vector theories with concatenation and extraction have been shown to be useful and important for hardware verication. We h a v e implemented an extended theory which includes arithmetic. Although deciding equality i n s u c h a theory is NP-hard, our implementation is e cient for many practical examples. We believe this to be the rst such implementation which is e cient, automatic, and complete.
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IEEE Transactions on Computers, 2000
Built-In Self-Test (BIST) techniques constitute an effective and practical approach for VLSI circuits testing. BIST schemes are typically classified into two categories: offline and online. Input vector monitoring concurrent BIST schemes are a class of online techniques that circumvent the problems appearing separately in online and in offline BIST in a very effective way. The utilization of input vector monitoring concurrent BIST techniques provides the capability to perform testing at different stages, manufacturing, periodic offline (in special test mode), and concurrent online (in normal mode of operation). The input vector monitoring concurrent BIST schemes proposed so far have targeted either exhaustive or pseudorandom testing separately. In this paper, a novel input vector monitoring concurrent BIST scheme based on a precomputed test set is presented. The proposed scheme can perform both concurrent online and offline testing; therefore, it can be equally well utilized for manufacturing and concurrent online testing in the field. The applicability of the scheme is validated with respect to the hardware overhead and the time required for completion of the test in benchmark circuits. To the best of our knowledge, the proposed scheme is the first to be presented in the open literature based on a precomputed test set that can perform both concurrent online and offline testing.
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Input vector monitoring concurrent built-in self test (BIST) schemes perform testing during the normal operation of the Random Access Memory without imposing a need to set the RAM offline to perform the test. These schemes are evaluated based on the hardware overhead and the concurrent test latency (CTL), i.e., the time required for the test to complete, whereas the circuit operates normally. In this brief, we present a novel input vector monitoring concurrent BIST scheme, which is based on the idea of monitoring a set (called window) of vectors reaching the circuit inputs during normal operation, and the use of a static-RAM-like structure to store the relative locations of the vectors that reach the circuit inputs in the examined window; the proposed scheme is shown to perform significantly better than previously proposed schemes with respect to the hardware overhead and CTL tradeoff..