A Continuous-Time Delta-Sigma Modulator for RF Subsampling Receivers (original) (raw)
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Preliminary Design and Comparative Analysis Between Different DT Sigma-Delta Modulators
Sigma-Delta analog-to-digital converters (ADCs) are known for providing high resolutions when compared to other ADC architectures. They are composed of a sigma-delta modulator and a digital decimation filter. This work focuses is in the high-level design of discrete-time sigma-delta modulators (DT-SDMs) whereas the design and implementation of first and second-order modulators are analyzed using Matlab. A complete performance analysis of each modulator is described using the cascade of integrators in feedback (CIFB) structure. It is worth mentioning that our study has a focus on medium bandwidth (BW) applications, as such audio applications. Besides, we target low-voltage operations. This work is at an early stage, thus only first and second-order modulators are investigated. This work considers a BW of 24 kHz, a sampling frequency of 6.144 MHz, and oversampling (OSR) of 128. Index Terms-sigma-delta modulators, sigma-delta ADC, DT-SDM CIFB structure.
Multirate double-sampling hybrid CT/DT sigma-delta modulators for wideband applications
2009
As the sampling frequency in modulators is upper limited by the amplifier bandwidth and power consumption, sigma-delta modulators should operate with low oversampling ratios (OSRs) in broadband applications. But, the modulator accuracy is reduced by lowering the OSR. Multirate signal processing and double-sampling have been proven appropriate techniques for preventing this effect and also lowering the power consumption in discrete-time modulators. In this paper, both of these techniques are simultaneously used to achieve power efficient hybrid CT/DT sigma-delta modulators.
Design and Implementation of Low-Oversampling Delta Sigma Modulators for High Frequency Applications
— The key factor making Delta-Sigma modulators (DSM) one of the most popular components in modern electronic circuits is its high linearity. This is achieved by using a high oversampling ratio which is unfortunately the limiting factor towards its application in high frequency circuits. The necessity of high processing speed and power, the increased cost and complexity and wastage of available bandwidth are some of the significant demerits of using a high oversampling ratio. This paper suggests that the delta sigma modulators require a high frequency processing and not high oversampling ratio. A parallel structure to perform the high frequency processing along with an adaptive method to improve the signal quality at the output is proposed. The suggested technique allows the simultaneous execution of fast and complex computations required for wireless systems. The analysis is performed using MATLAB simulations and the results claim a reduction in oversampling ratio by a factor of 16 while keeping the same signal to noise ratio. The proposed architecture is implemented on a field-programmable gate array (FPGA) board which is then validated with a code division multiple access signal. The output signal bandwidth is observed to be increasing four times without any increase in the sampling frequency. Keywords—Delta–sigma modulation, oversampling, parallel processing, field-programmable gate array (FPGA).
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000
The oversampling requirement in a delta-sigma modulator (DSM) is considered one of the limiting factors toward its employment in current high-frequency applications, such as wireless software defined radio (SDR) systems. This paper advances that the critical requirement for DSMs is high-frequency processing and not a high-oversampling ratio. A single-bit semiparallel processing structure to accomplish the high-frequency processing is proposed in this paper. Using the suggested low-oversampling digital DSM architecture, highspeed, high-complexity computations, which are normally required for wireless applications, are executed simultaneously. This facilitates the design of embedded SDR multistandard transmitters using commercially available digital processors. The most favorable application of the proposed single-bit DSM is to build an radio frequency transmitter that includes a one-bit quantifier with two-level switching power amplifier for both high linearity and high efficiency. Performance analysis is carried out by using MATLAB simulations, which shows a reduction of the oversampling ratio by a factor of 16 (for a baseline oversampling ratio of 256) with the same signal-to-noise ratio (SNR). The proposed DSM is also implemented on a field-programmable gate array (FPGA) board and its performance is validated by using a code division multiple access signal. The bandwidth of the output signal is increased four times without increasing the processing frequency. Simultaneously, quality of the output signal remains the same but FPGA resource usage is increased by a factor of three.
Delta-sigma modulators using frequency-modulated intermediate values
IEEE Journal of Solid-State Circuits, 1997
This paper describes a new first-and second-order delta-sigma modulator concept where the first integrator is extracted and implemented by a frequency modulator with the modulating signal as the input. The result is a simple delta-sigma modulator with no need for digital-to-analog converters, allowing straightforward multi-bit quantization. Without the frequency modulator, the circuit becomes a frequency-to-digital converter with delta-sigma noise shaping. An experimental first-and second-order modulator have been implemented in a 1.2-¼m standard digital CMOS process and the results confirm the theory. For the first-order modulator an input signal amplitude of 150mV resulted in a SQNR of ³115dB at 2MHz sampling frequency and signal bandwidth 500Hz.
Oversampled delta-sigma modulators: Analysis, applications and novel topologies
2003
new method to obtain efficient architectures for time-interleaved Delta-Sigma modulators. Additionally, a novel parallel conversion technique, which we have dubbed as the "Zero-Insertion Time-Interleaving" concept is also proposed. In this approach, the input only needs to be sampled at the operating frequency of the parallel channels. Thus, the high sampling rate input multiplexer involved in the regular Time-Interleaved approach is completely eliminated resulting in further significant reductions in the hardware complexity. Such a multiple channel Delta-Sigma modulator may be very useful for implementing high-resolution converters for wide bandwidth input signals, at the expense of moderate increase in the hardware cost.
2004
This paper presents the design of a second order, single-bit, analog-to-digital, continuous-time Delta-Sigma Modulator (CT-M) that can be used in wireless CDMA receivers. The CT-M samples at 2 GHz, consumes 18 mW at 1.8 V and has a 79 dB signal-to-noise ratio (SNR) over a 1.23 MHz bandwidth. The CT-M was fabricated in a 0.18 m, 1poly, 6-metal, CMOS technology and has an active area of approximately 0.892 mm 2. The M's critical performance specifications are derived from the CDMA receiver specifications. Index Terms-Analog-digital conversion, Code division multiple access, Continuous time delta-sigma modulation, CMOS, High-speed integrated circuit I. INTRODUCTION Recently, a family of receiver architectures, often called digital radio receivers, has gained interest in the wireless communications industry. Such architectures include the zero intermediate frequency (IF) (ZIF) receiver and the complex low IF (CLIF) or Weaver architecture receiver [1]. Unlike superheterodyne architectures that perform channel filtering and automatic gain control (AGC) after the first down conversion and digitize the received signal after a second down conversion, digital radio architectures digitize the received signal after a single down conversion and perform AGC and channel filtering digitally. As a result, digital radio receivers rely mainly on digital circuitry, and can therefore be programmed to operate as multimode receivers. Also, because the density of digital circuitry is far greater than that of RF circuitry, digital radio receivers can be fabricated on a single
Continuous-Time Bandpass Delta-Sigma Modulator for a Signal Frequency of 2.2 GHz
2009 German Microwave Conference, 2009
This paper presents a concept for a Continuous-Time Bandpass-Delta-Sigma Modulator (CT BPDSM) for class-S amplifiers. Class-S amplifiers are very efficient for signals with high dynamic range and are considered to be one possible replacement for conventional linear amplifiers in RF transmitters. A multi-feedback architecture with return-tozero (RZ) and half-return-to-zero (HRZ) pulses is chosen for the modulator. Noise considerations lead to a low noise transconductor with emitter degeneration. The loop filters consist of LC resonators with Q-enhancement. The effect of excess-loop-delay is mitigated by an optimized clock tree. For a 2.1 GHz input signal an SNR of 59 dB at a bandwidth of 20 MHz is expected. I.
Design of Multi-bit Sigma-Delta Modulators for Digital Wireless Communications
The ever advance of CMOS digital circuit process leads to the trend of digitizing an analog signal and performing digital signal processing as early as possible in a signal processing system, which in turn leads to an increasing requirement on analog-to-digital converter (ADC). A wireless transceiver is a such kind of signal processing system. Conventional transceivers manipulate (filter, amplify and mix) the signal mostly in analog domain. Since analog filters are difficult to design on-chip, the system integration level is low. Modern transceivers shift many of these tasks to digital domain, where the filtering and channel selection can be realized more accurately and more compactly. However the price for the high integration level is the critical requirement on the ADC, because the simplified analog part sends not only the weak signal but also the unwanted strong neighboring channel to the ADC. In order to digitize the needed signal in the presence of strong disturbances, a high dynamic-range and high-speed ADC is needed.