Multiple-Valued Logic Circuit Design and Data Transmission Intended for Embedded Systems (original) (raw)

2022, Cornell University - arXiv

Recently, the demand for portable electronics and embedded systems has increased. These devices need low-power circuit designs because they depend on batteries as an energy resource. Moreover, Multi-Valued Logic (MVL) circuits provide notable improvements over binary circuits in terms of interconnect complexity, chip area, propagation delay, and energy consumption. Therefore, this thesis proposes novel ternary circuits aiming to reduce the energy (Power Delay Product (PDP)) to preserve battery consumption. The proposed designs include eight ternary logic gates, three ternary combinational circuits, and six Ternary Arithmetic Logic Units (TALU). The ternary logic gates are seven unary operators of the ternary system (A 1 , A 2 ,Ā 2 , A 1 , 1.Ā n , 1.Ā p , and the Standard Ternary Inverter (STI)Ā), and Ternary NAND based on Carbon Nanotube Field-Effect Transistor (CNFET). Ternary combinational circuits, two different designs for Ternary Decoders (TDecoder) and Ternary Multiplexer (TMUX): (1) TDecoder1 using CNFET-based proposed unary operators and TDecoder2 using Double-Pass Logic (DPL) binary gates. (2) TMUX using CNFET-based proposed unary operators. And Ternary Arithmetic Logic Units are three different designs for Ternary Half-Adders (THA) and Ternary Multipliers (TMUL): (1) The first design uses the proposed TDecoder1, STI, and TNAND. (2) While the second design uses the cascading proposed TMUX. (3) As for the third design, it uses the proposed unary operators and TMUX. This thesis applies the best trade-off between reducing the number of used transistors, utilizing energy-efficient transistor arrangement such as transmission gate and applying the dual supply voltages (Vdd, and Vdd/2) to achieve its objective. The proposed designs are compared to the latest ternary circuits using the HSPICE simulator for different supply voltages, different temperatures, and different frequencies. Simulations are performed to prove the efficiency of the proposed designs. The results demonstrate the advantage of the proposed designs with a reduction over 73% in terms of transistors count for the THA and over 88%, v 99%, 98%, 84%, 98%, and 99% in energy consumption for the STI, TNAND, TDecoder, TMUX, THA, and TMUL, respectively. Moreover, the noise immunity curve (NIC) and Monte Carlo analysis for major process variations (TOX, CNT Diameter, CNT's Count, and Channel length) were studied. The results confirmed that the third proposed THA3 and TMUL3 had higher strength and higher noise tolerance, among other designs. In addition, the second objective is using ternary data transmission to improve data communications between computer hosts. Also, this thesis proposes a bi-directional circuit that contains two converters: (1) A binary-to-ternary converter and (2) a ternary-to-binary converter. Finally, logical analysis and simulation results prove the merits of the approaches compared to existing designs in terms of transistor count, reduced latency, and energy efficiency. vi Contents Contents vii List of Tables xi List of Figures xiv Abbreviations xvii Symbols xix Appendix B CNFET-Based Designs of Ternary Half-Adder using a Novel "Decoderless" Ternary Multiplexer based on Unary Operators