Dynamic power estimation for deep submicron circuits with process variation (original) (raw)
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This paper presents a efficient approach for the estimation of signal activity figures based on a gate level description of a digital circuit. Exploiting an event oriented simulation system a methodology for calculating very accurate power estimates for digital circuits is presented. A calibration scheme for characterizing the power dissipation of logic gates based on a few key parameters will be outlined. The proposed method proves that the use of an event oriented simulation system calibrated with these gate specific parameters allows power estimations which are comparable to transistor level (SPICE) simulation accuracy. This is essential for the analysis of large circuits, because the proposed event driven simulation system is about 10000 times faster than transistor level simul ation. Experimental results and benchmarks are presented which demonstrates significant improvements in terms of performance, accuracy and flexibility of this approach compared to other state of the art power estimation met hods.
Gate-level power estimation using tagged probabilistic simulation
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 1998
In this paper, we present a probabilistic simulation technique to estimate the power consumption of a CMOS circuit under a general delay model. This technique is based on the notion of a tagged (probability) waveform, which models the set of all possible events at the output of each circuit node. Tagged waveforms are obtained by partitioning the logic waveform space of a circuit node according to the initial and final values of each logic waveform and compacting all logic waveforms in each partition by a single tagged waveform. To improve the efficiency of tagged probabilistic simulation, only tagged waveforms at the circuit inputs are exactly computed. The tagged waveforms of the remaining nodes are computed using a compositional scheme that propagates the tagged waveforms from circuit inputs to circuit outputs. We obtain significant speed up over explicit simulation methods with an average error of only 6%. This also represents a factor of 2-32 improvement in accuracy of power estimates over previous probabilistic simulation approaches.
Logic Picture-Based Dynamic Power Estimation for Unit Gate-Delay Model CMOS Circuits
Circuits and Systems, 2013
In this research, a fast methodology to calculate the exact value of the average dynamic power consumption for CMOS combinational logic circuits is developed. The delay model used is the unit-delay model where all gates have the same propagation delay. The main advantages of this method over other techniques are its accuracy, as it is deterministic and it requires less computational effort compared to exhaustive simulation approaches. The methodology uses the Logic Pictures concept for obtaining the nodes' toggle rates. The proposed method is applied to well-known circuits and the results are compared to exhaustive simulation and Monte Carlo simulation methods.
Power modeling for high-level power estimation
Very Large Scale Integration (VLSI) …, 2000
In this paper, we propose a modeling approach that captures the dependence of the power dissipation of a combinational logic circuit on its input/output signal switching statistics. The resulting power macromodel, consisting of a single four-dimensional table, can be used to estimate the power consumed in the circuit for any given input/output signal statistics. Given a low-level (typically gate-level) description of the circuit, we describe a characterization process by which such a table model can be automatically built. The four dimensions of our table-based model are the average input signal probability, average input transition density, average spatial correlation coefficient and average output zero-delay transition density. This approach has been implemented and models have been built for many benchmark circuits. Over a wide range of input signal statistics, we show that this model gives very good accuracy, with an RMS error of about 4% and average error of about 6%. Except for one out of about 10,000 cases, the largest error observed was under 20%. If one ignores the glitching activity, then the RMS error becomes under 1%, the average error becomes under 5% and the largest error observed in all cases is under 18%.
1999
This paper presents a efficient approach for the estimation of signal activity figures based on a gate level description of a digital circuit. Exploiting an event oriented simulation system a methodology for calculating very accurate power estimates for digital circuits is presented. A calibration scheme for characterizing the power dissipation of logic gates based on a few key parameters will be outlined. The proposed method proves that the use of an event oriented simulation system calibrated with these gate specific parameters allows power estimations which are comparable to transistor level (SPICE) simulation accuracy. This is essential for the analysis of large circuits, because the proposed event driven simulation system is about 10000 times faster than transistor level simul ation. Experimental results and benchmarks are presented which demonstrates significant improvements in terms of performance, accuracy and flexibility of this approach compared to other state of the art power estimation met hods.
Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model
Journal of Advanced Research, 2015
ABSTRACT Dynamic power estimation is essential in designing VLSI circuits where many parameters are involved but the only circuit parameter that is related to the circuit operation is the nodes’ toggle rate. This paper discusses a deterministic and fast method to estimate the dynamic power consumption for CMOS combinational logic circuits using gate-level descriptions based on the Logic Pictures concept to obtain the circuit nodes’ toggle rate. The delay model for the logic gates is the real-delay model. To validate the results, the method is applied to several circuits and compared against exhaustive, as well as Monte Carlo, simulations. The proposed technique was shown to save up to 96% processing time compared to exhaustive simulation.
Power Macromodeling For High Level Power Estimation
Proceedings of the 34th Design Automation Conference, 1997
A modeling approach is presented that captures the dependence of the power dissipation of a combinational logic circuit on its input/output signal switching activity. The resulting power macromodel, consisting of a single three dimensional table, can be used to estimate the power consumed in the circuit for any given input/output signal statistics. Given a low-level (typically gatelevel) description of the circuit, we describe a characterization process by which such a table model can be automatically built. In contrast to other proposed techniques, this can be done for any given logic circuit without any user intervention, and applies to all possible input/output signal statistics; it does not require one to construct specialized analytical equations for the power dissipation. The three dimensions of our table-based model are the average input signal probability, average input transition density, and average output zero-delay transition density. This approach has been implemented and models have been built for many benchmark circuits. Over a wide range of input signal statistics, we show that this model gives very good accuracy, with an RMS error of under about 6%.
2019
With the technology scaling down to sub-50 nm regime, the necessity of process variation aware estimation of Leakage Power is emphasized for robust digital circuit design. Variations in Leakage power results in a large increase in the variation of total power dissipation. This paper presents a Regression based estimation of leakage powers and total power dissipation in nanoscale standard cell-based designs that show an impressive speed-up advantage with respect to analog SPICE-level simulation. We propose a statistical variation aware estimation model through a Multivariate Linear Regression (MLR) and Multivariate Polynomial Regression (MPR) techniques. Exhaustive tests report shows MPR technique outperforms MLR technique in estimating the leakage and total power for the targeted 16 nm CMOS technology with negligible error (<1%). The proposed methodology works as black box i.e. equally valid for 16 nm, 22 nm and 45 nm technology nodes.
Accurate and fast power estimation of large combinational circuits
A novel probabilistic method to estimate the switching activity of a logic circuit under a real delay gate model, is introduced. Based on Markov stochastic processes and generalizing the basic concepts of zero delay-based methods, a novel probabilistic model to estimate accurately the power consumption, is developed. More specifically, a set of new formulas, which describe first-order temporal correlation, under real delay model, are derived. The chosen gate model allows accurate estimation of the functional and spurious (glitches) transitions, leading to accurate power estimation. The proposed approach manipulates efficiently large circuits employing a new partitioning heuristic, which estimates the switching activity with reduced computational complexity. Comparative study and analysis of benchmark circuits demonstrates the accuracy and efficiency of the proposed method.
An Empirical Methodology for Power Analysis of CMOS Integrated Circuits
Elektronika ir Elektrotechnika, 2017
Energy consumption is becoming one of the most significant aspects of CMOS Integrated Circuits (IC), especially for those applied in embedded devices whose autonomy depends upon battery lifespan. Therefore, an empirical methodology for determination of power and energy dissipation may provide valuable information to IC designers, as well as software developers, which could impact design process and lead to more energy-efficient solutions. This paper presents a novel methodology for determination of static and dynamic components of energy dissipation for those CMOS ICs that do not support turning off clock distribution entirely, but provide ability to divide a clock frequency. For that purpose, we used an Eclipse based IDE that provides a user friendly interface for dividing a clock frequency on ultra-low power embedded DSP platform, which was used as a target device. Measurements were performed using a true RMS multimeter. Various experiments were conducted using different scenarios, on single and multi cores, in order to validate the described empirical methodology, and the outcome confirmed what was expected, that the obtained results are stable and accurate.