Third-order Single-bit Sigma Delta modulator structure for an RF reception chain for a LTE network (original) (raw)

Design of Multi-bit Sigma-Delta Modulators for Digital Wireless Communications

The ever advance of CMOS digital circuit process leads to the trend of digitizing an analog signal and performing digital signal processing as early as possible in a signal processing system, which in turn leads to an increasing requirement on analog-to-digital converter (ADC). A wireless transceiver is a such kind of signal processing system. Conventional transceivers manipulate (filter, amplify and mix) the signal mostly in analog domain. Since analog filters are difficult to design on-chip, the system integration level is low. Modern transceivers shift many of these tasks to digital domain, where the filtering and channel selection can be realized more accurately and more compactly. However the price for the high integration level is the critical requirement on the ADC, because the simplified analog part sends not only the weak signal but also the unwanted strong neighboring channel to the ADC. In order to digitize the needed signal in the presence of strong disturbances, a high dynamic-range and high-speed ADC is needed.

Sigma-delta modulators for high-resolution and wide-band A/D converter applications

Microelectronics Journal, 1994

High-resolution and wide-band sigma-delta (∑Δ) A/D converters are based on high-order single-stage or cascade modulators and, more recently, also on multibit topologies. This paper reports a comparative study of the most promising modulator topologies available today, paying special attention to a new class of cascade multibit topologies that we have developed which do not require multibit D/A converters. Comparisons are made in terms of design and implementation complexity, sensitivity to amplifier dc-gain and matching between components, thermal noise, amplifier slew-rate and bandwidth, and D/A converter linearity. Design examples are given showing that 12-bit, 14-bit and 16-bit ∑Δ A/D converters with 4 MHz, 1 MHz and 150kHz output rates respectively are possible using state-of-the-art silicon technologies.

Design of Second Order Discrete Time Sigma Delta Modulator for High Resolution Applications

2017

Aim of This work is to Design a second order discrete time sigma delta modulator for low frequency high resolution applications, which can be used in data converters (sigma delta ADC) where high resolution is required for more accuracy in signal processing’s. A real world is analogue but easier to process digital data ex: speech, image processing’s. Analog signal contains too much unnecessary data ADC samples the data and splits into finite information. Sigma delta ADC is very much suitable for less area low frequency and high resolution data conversions. Now the aim is to design a sigma delta modulator in which these parameters plays major role 1) resolution 2) order 3) OSR 3) power consumption 4)SNR 5)SNDR 6)dynamic Range. This design is carried out with the 180nM CMOS technology at an operating voltage of ±700mV, and the results are tested with the help of Cadence Virtuoso Spectre Circuit Simulator.

Preliminary Design and Comparative Analysis Between Different DT Sigma-Delta Modulators

Sigma-Delta analog-to-digital converters (ADCs) are known for providing high resolutions when compared to other ADC architectures. They are composed of a sigma-delta modulator and a digital decimation filter. This work focuses is in the high-level design of discrete-time sigma-delta modulators (DT-SDMs) whereas the design and implementation of first and second-order modulators are analyzed using Matlab. A complete performance analysis of each modulator is described using the cascade of integrators in feedback (CIFB) structure. It is worth mentioning that our study has a focus on medium bandwidth (BW) applications, as such audio applications. Besides, we target low-voltage operations. This work is at an early stage, thus only first and second-order modulators are investigated. This work considers a BW of 24 kHz, a sampling frequency of 6.144 MHz, and oversampling (OSR) of 128. Index Terms-sigma-delta modulators, sigma-delta ADC, DT-SDM CIFB structure.

A/D Conversion Using Asynchronous Delta-Sigma Modulation and Time-to-Digital Conversion

IEEE Transactions on Circuits and Systems I: Regular Papers, 2010

An analog-to-digital conversion (ADC) scheme based on asynchronous 16 modulation and time-to-digital conversion is presented. An asynchronous 16 modulator translates the analog input to an asynchronous duty-cycle modulated signal. Next, the edge locations are digitally measured using a time-to-digital converter (TDC). This information is then digitally processed into a conventional digital signal. The performance of this novel ADC scheme is theoretically analyzed and verified with simulations. With the proposed digital demodulation algorithm, 11-bit resolution can be obtained with an overcycling ratio (OCR) of only four, which is suitable for high bandwidth applications such as very high bit-rate digital subscriber line (VDSL). When a higher OCR can be tolerated, a gated ring-oscillator (GRO) TDC with an inherent first-order noise shaping property is suggested in combination with a digital continuous-time moving-average (CTMA) filter. This allows for resolutions in excess of 13 bits, which is suitable for ADSL2+. The proposed technique shifts the complexity toward the digital domain, leading to more compact ADC and reduced power consumption, and is, therefore, particularly suited for ADC in ultralow-voltage nanometer technologies that are used for high-speed data communication applications. Index Terms-Analog-to-digital conversion (ADC), asynchronous delta-sigma modulation (ADSM), continuous-time moving-average (CTMA) filter, demodulation, gated ring-oscillator (GRO), time-to-digital conversion. I. INTRODUCTION A LONG WITH THE downscaling of the minimum feature size of modern CMOS technologies, the supply voltage is scaled down accordingly to reduce power dissipation. Reducing the supply voltage, however, increases the design effort and the power consumption for analog circuits even when the required performance is kept constant [1]. Therefore, increasing effort is spent to shift the analog complexity toward the digital domain in an attempt to reduce power consumption while increasing speed and accuracy. Specifically for analog-to-digital Manuscript

On Design a High Speed Sigma Delta DAC Modulator for a Digital Communication Transceiver on Chip

2008

The operation speed in the digital circuit is very important for accomplishing the performance which can satisfy different communication protocol specifications. This paper therefore addresses this problem by using a parallel structure for radio frequency modulation at system level and by using redundancy coding for speed improvement at register transfer level. Due to the flexibility of the sigma delta structure, the designs can trade off between bandwidth and signal-to-noise ratio (SNR) to adapt to different digital communication protocol specifications. A 4 th order structure can e.g. achieve 6.5 MHz single-side bandwidth (SBW) with 99 dB SNR at base band; or it can achieve 26 MHz double-side bandwidth with 73 dB SNR. Moreover, if latches are used, the sampling frequency can reach 1.4 GHz in a 5 th order 2bit structure implemented in a 0.13 μm ASIC, which can achieve 29 MHZ SBW with 81 dB SNR. These implementations occupy very little area as demonstrated in the data obtained from synthesis in a 0.13 μm CMOS standard cell library. These sigma delta structures therefore can be integrated in a SOC for different digital communication transceivers effectively.

I-bit sigma delta analog to digital converter for multistandard GSM/UMTS radio receiver

2004 IEEE International Conference on Industrial Technology, 2004. IEEE ICIT '04., 2004

This paper deals with specification and design methodology of Analog to Digital Converter (ADC) stage for high dynamic range wide band Multi-standard Radio receiver. To respect high resolution requirements a Sigma Delta (Σ∆) Σ∆) Σ∆) Σ∆) modulator based ADC is proposed. A High dynamic range low complexity 1-bit Sigma Delta modulator is designed to guarantee high linearity for GSM/UMTS signals. Hence, a stable 3 rd order 1-bit low-pass Σ∆ Σ∆ Σ∆ Σ∆ modulator is defined. Simulation results show more than 90 dB dynamic ranges for GSM and 60 dB for UMTS.

Design Considerations of Data Converters for Industrial Technology

2019 International Conference on IC Design and Technology (ICICDT), 2019

This paper presents circuit design considerations of high resolution data converters applied for industrial technology, some important design issues related to filter in analog-to-digital converters (ADCs) are discussed. Whole design flow about filter is given in this work and the design considerations mentioned in this paper are useful for the industrial practice and applications of high resolution ADC, finally, a practical design is illustrated with discussion of ΣΔ modulator.

Modeling and characterization of sigma-delta analog-to-digital converters

IEEE Transactions on Instrumentation and Measurement, 2003

This paper deals with a comprehensive approach to metrological research on sigma-delta analog-to-digital converters based on a framework of international cooperation. Problems related to modeling and experimental testing of high-performance sigma-delta modulators are highlighted. Results of simulation and experimental tests carried out on a prototype of fifth-order sigmadelta modulator are discussed by emphasizing the effectiveness of the international research cooperation in efficiently reaching significant results.